Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
878
questions
0
votes
1
answer
919
views
DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
- 1
1
vote
0
answers
48
views
Does "field electron emission" used in EEPROM work better than "hot-carrier injection" in NOR Flash?
After deeping research based on my another question, I continued comparing Flash and EEPROM based on wikipedia comparison table.
From wikipedia about the Flash memory:
Programming
the source-drain ...
- 183
1
vote
1
answer
55
views
Is it possible to use a MOS 6502 with a AE29F2008?
I wanted to buy a MOS 6502, but before that, wanted to know if it is possible to interface it with an AE29F2008 memory (recovered from a PC). The problem is that the AE29F2008 has three address pins ...
- 27
0
votes
1
answer
65
views
Tsi107 PowerPC Host Bridge Vs Processor
I a confused regarding the difference between a powerPc host bridge and a processor. According to the host bridge datasheet, it can be programmed, and it has interrupt generation and handling, and ...
- 671
0
votes
1
answer
179
views
What are the options to interface Altera or Xilinx FPGA with a microprocessor or microcontroller?
I am trying to design a system which has some sensors connected to an FPGA and want to transfer the sensor data from the FPGA to a microprocessor like NXP IMX. I am new to FPGA and would like to know ...
- 75
11
votes
8
answers
5k
views
What mechanism does CPU use to know if a write to RAM was completed?
How does CPU know that a write to RAM was successful, like how does a faster CPU know that data was successfully written to a slower RAM?
You're free to mention any system architecture because I'm not ...
- 191
0
votes
0
answers
233
views
Can a PCI bus master access a device mapped in cpu memory space
If a PCI bus master can access memory space just as cpu can, can it put an address on the memory bus of the cpu that actually triggers a memory mapped I/O device to respond to that address.
(As if the ...
- 191
1
vote
1
answer
186
views
Using SRAM Macro for simulation and synthesis
I got my hands on this ARM Artisan memory compiler for generating SRAMs. I generated .v and .lib files from it to carry out RTL ...
- 319
0
votes
1
answer
133
views
How does data reach peripherals in STM32H7xx?
I'm trying to understand bus interconnection matrix in stm32h7xx. Here is a capture of the H753's one:
In particular, I'm wondering how a data buffer located in DTCM would reach the SPI1's tx ...
- 1,259
0
votes
1
answer
90
views
How to debug modbus rtu address space problems? [closed]
I have an "Ewon Flexy server" and an "IMO SD1 Inverter" connected via Modbus RTU RS485.
I can change some of the parameters with Flexy interface and observe the change in the ...
- 188
0
votes
1
answer
1k
views
RISC-V byte load and store
I have the confusion in the following RISC V programming statements. Can someone explain that why does the contents of s0 in the last comment shown. shouldn't it be 0x00000180 the same as we are not ...
- 671
4
votes
1
answer
265
views
What are the possible implementations of LUT on silicon?
I'm looking for the possible ways to implement a LUT. The only way I know is to use Flip Flops to store the outputs and a MUX to select the output using the input as a select signal. Is there any ...
- 51
0
votes
2
answers
69
views
Faulty address line [closed]
how to find address line fault in microcontroller if microcontroller connected to external memory through address line? if given one line in address is faulty how to pinpoint the particular line ...
- 1
0
votes
0
answers
43
views
Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
- 137
0
votes
0
answers
136
views
SDHC card is read as SD by READ_OCR
I'm trying to use 32 GiB SDHC card in SPI mode but I have problem with initialization. I send SD_SEND_OP which finally returned 0x00 but it doesn't have CCS bit set:
...
- 512