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Electrical Engineering
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Martel's user avatar
Martel's user avatar
Martel
  • Member for 5 years, 1 month
  • Last seen more than a week ago
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Top posts
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13
In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?
Nov 12, 2021
10
Does the SPI protocol specify how many clock pulses a master device should send to the slave?
Nov 9, 2021
6
Vivado constraints wizard suggests a lot of nonsense generated clocks
Oct 11, 2022
5
Don't understand MOSFET as amplifier
Aug 20, 2019
5
Charge pump has an unexpected voltage drop with a 1K load
Apr 30, 2021
4
Don't understand the current direction in a flyback diode circuit
Jan 9, 2021
3
Is it necessary to take into account the actual state of a combinational circuit's signals to calculate its maximum delay?
Apr 2, 2022
3
Ternary operator doesn't work in Icarus Verilog
Dec 30, 2021
3
What is "voltage output swing from rail" in a TI op-amp datasheet?
May 12, 2021
2
Don't understand why this clock interaction is unsafe
Sep 18, 2022
Top network posts
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16
Is it ok to upvote everyone that answers my question, or leaves a comment, just to appreciate the time they spent writing?
6
Understanding the past growth of an ETF
6
How to find the trading costs in an ETF prospectus
6
Can fundamental analysis be applied to market indexes as if they were single stocks/bonds?