Questions tagged [asic]
An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.
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Clock domain crossing without synchronisers
I am (re)designing an SPI slave module in VHDL for an ASIC. The SPI domain is faster than the main clock domain (~10MHz and ~1MHz), so the SPI state machine operates in the SPI domain. The previous ...
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Reconciling phase shift error of length-tuned structures in 81-86GHz I/Q direct down-converter ASIC with datasheet specifications
I'm watching a video on reverse engineering a GaAs 81-86GHz I/Q down-converter ASIC. The relevant section of the video for this question is 10 minutes onwards, but watching the video isn't necessary ...
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What is name of the technique where we create modules to help us test our digital design?
In my FPGA design project, I created a few modules that can be used to emulate output from another module. Then there were modules that would inject erronous data or signals that signify errors. By ...
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Pin vs Port terminology in SDC
In SDC (Synopsys Design Constraints), set_driving_cell is said to be used to model the drive resistance of the cell driving the input port. I'm confused by the word ...
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Standard cell design flow in an ASIC design flow
I have a question regarding the standard cell design flow in an ASIC design flow.
That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured ...
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What are horizontal and vertical track pitches?
I was experimenting on OpenLANE with Sky130 PDK and below is the tracks.info file. I learned from a workshop that the values pertain to the track pitches as ...
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Why don't 2 flip-flop synchronizers have a reset?
This is similar to this question, asking if a reset is needed in a 2 flip-flop synchronizer. The answer to that question was: "no, not necessarily".
So, my question is:
Why do almost all of ...
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Why is a reset with asynchronous assert safe?
As far as I understand, a reset with asynchronous assert, synchronous de-assert is considered absolutely safe. I understand that this prevents metastability at the output of a flip-flop using that ...
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Does an ASIC have an instruction set? [closed]
Does an Application Specific Integrated Circuit have an instruction set like a CPU?
If yes, then that would contradict the statement "ASIC is faster than CPU" because having an instruction ...
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Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?
There are several techniques that can be used to transfer data between two asynchronous clock domains. For a few bits, and depending on direction of data between the two clock domains, one could use ...
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RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?
Given the below scenario, which is a reset-domain-crossing violation :
Can it be resolved using some reset synchronization strategy?
Is such design considered bad to begin with, i.e. need to avoid ...
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ASIC Hardware cost
Why is multiplication with a fixed coefficient cheaper in ASIC as compared to variable multiplication?
Would it be faster using an FPGA inferring a DSP Slice?
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NEC asic information from around 1990
I'm looking for datasheets with specification for the NEC ASIC/Gate Arrays from around 1990.
More preciselly, any information with specifications of their ASIC/Gate Array lines.
I would like to known ...
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8bitworkshop(verilog) to terminal transition
I have been working through very basic Verilog code examples at https://8bitworkshop.com (supports a book I am following). I understand there are a few good online options available and will pursue ...
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Is it possible for an SoC to have a built-in SSD?
Is it possible to have an SoC that includes an SSD on-chip, or are there technical constraints that prevent that? What are those technical constraints, if any?
