All Questions
Tagged with verification verilog
14
questions
1
vote
1
answer
71
views
How to connect multiple TLM ports to UVM Sequencer?
There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
- 21
0
votes
2
answers
373
views
When using Cocotb, should I be using FallingEdge to set and assert values?
I'm attempting to use Cooctb to verify a simple Verilog counter with a reset:
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- 227
-2
votes
1
answer
2k
views
Sign Extension in Verilog [closed]
what is the difference between the following 3 sign extensions
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- 99
0
votes
1
answer
740
views
SystemVerilog Assertions syntax error unexpected |-> [closed]
I'm starting to use SVAs for formal verification.
I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?):
as I do ...
- 327
2
votes
2
answers
88
views
Transaction randomization succeeds, yet values do not meet constraints
In the following code, I attempt to randomize the transaction which contains a dynamic array 'PhyRB', with the constraint that each element in the array is less than 'ResBlks' value. Please note that ...
3
votes
1
answer
135
views
Best way to structure Verilog module to allow for simulation clocks
Quick question that I am likely missing an obvious solution for. I have a relatively simple Verilog design which I'll call taco, where the top-level design entity is taco_top (because I'm writing this ...
- 6,376
1
vote
1
answer
574
views
System Verilog Coverpoint Bin for everything else that is counted towards coverage calculations
Setting a bin to default grabs everything else in the coverpoint, but the default bin is ignored in coverage calcuations. Is there anything similar to default that I can use for syntax that will ...
- 11
0
votes
1
answer
8k
views
How to measure time difference between 2 signal changes in verilog?
There are two signals sig, enable - and I wanted to find the time difference after which enable toggles after sig falls. ( >Sig Low to Enable toggle< time)
I understand that always@() block can't ...
6
votes
2
answers
1k
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Is there a "standard" way to verify HDL of a state machine?
State machines are a pattern that is used very often in writing synchronous designs. They serve as the controllers in the design. So, is there a standard way to verify them if they are written using ...
- 12k
0
votes
1
answer
50
views
What does this sentence mean in this question (simulator can handle X inputs)?
In my book, one question requires me to find the verification sequence for a circuit. From what I understand, verification sequence must be such that every path is traversed.
Then the book ...
- 143
1
vote
1
answer
2k
views
Error Loading Design Unresolved Reference
DUT:
module ANDgate(a, b, c);
input a;
input b;
output c;
assign c = a & b;
endmodule
TESTBENCH: Without task
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1
vote
1
answer
944
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Where should I instantiate the DUT object, in the testbench file or in the task?
I am making a testbench in Verilog where it will call different test cases from different modules: each module, one test case/task.
Where should I instantiate the DUT object, in the testbench file or ...
-1
votes
1
answer
4k
views
Running UVM example on MODELSIM - ALTERA 10.1d
I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool.
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- 141
16
votes
8
answers
17k
views
What is the difference between testing and verification?
Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction.
To ...
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