Questions tagged [netlists]
The netlists tag has no usage guidance.
14
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How can a designer be sure to authorize only legit ICs? How is performed? How are cloned ICs prevented to be activated?
The above diagram is from the IC Activation (locking/unlocking) slide of Fighting against theft, cloning and counterfeiting of integrated circuits by Lilian Bossuet Associate Professor, CNRS Chaire of ...
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Netlisting errors in Pspice "ERROR(ORNET-1163): Unable to create netlist file."
I'm simulating a simple BiCMos Darlington Circuit from the "Analysis and Design of Analog Integrated Circuits" book in Pspice Orcad Software. I don't know why when I'm trying to run the ...
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Errors in Schematic made in Altium Designer
I am using Altium Designer as ECAD tool for first time to create the schematics. There are few errors which are popping up and I don't know how to get rid of those errors.
First one is regarding HI ...
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Help on LM324 SUBCKT model [closed]
I'm newbie in ngspice and having a hard time to understand the LM324 models downloaded from various sources.
Made an example with 4 different instances to demonstrate my doubt.
The idealOpAmp works as ...
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1
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66
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Understanding netlist IF statements
I`m reviewing this paper on how to do SPICE modelling for an FG transistor: https://digital-library.theiet.org/content/journals/10.1049/el.2011.0458
Inside there is a figure provided:
I`m completely ...
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How to set sizes of ASAP7nm transistors in NGSPICE (or HSPICE)
I want to write a netlist of a basic two-stage amplifier using the ASAP 7nm predictive technology and simulate it using NGSPICE.
There are some useful instructions and files in this question.
However, ...
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145
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Do HDL synthesizers "optimize code", more or less as compilers do?
I'm implementing a pipelined CPU in SystemVerilog. I need to propagate datapath signals from one pipeline stage to the next but, of course, not all stages produce the same number of signals.
To keep ...
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Missing nets in PCB editor
I designed a schematic in KiCad 7.0.8, have verified that I have foot prints assigned to all components and when I hit F8, it switches over to the PCB editor, I get the "Changes To Be Applied&...
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SPICE netlist standard?
Is there an official IEEE or other standard for SPICE netlists? I have tried to find one and not found it.
My friends and I are interested in building parsers of netlist files as input. I understand ...
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Are the Spice models for the TL082 and TL084 wrong?
I am working on a simple phase-lag circuit schematic using LT Spice, and, due to some project specifications, would like to simulate the behavior of the circuit specifically with FET-Input Operational ...
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How do I perform a basic op-amp DC sweep analysis in LTspice?
I want to simulate a simple approximation of an op-amp with an LTspice netlist, as required by my professor.
Circuitlab allowed me to confirm that this circuit outputs -2×Vin at node 003, but I can't ...
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How can I DC analyze these values in netlist simulation
For my lab report I have to DC analyze a circuit for these specific VDD values.
Is there any way to get simulation output for just these values? Because when I write
.DC VDD 0.2V 10V 0.2V or .DC VDD 0....
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610
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Interacting with SPICE netlists using PySpice
I am trying to come up with a generic Python program that I can use to simulate different simple electronic circuits. The actual idea is to programmaticaly change parameters and do Montecarlo analyses....
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Netlist compatibility between Ngspice & LTspice
I am running LTspice in batch mode on my Windows. However, I am now migrating to Linux, where the alternative to LTspice is Ngspice. The problem I am facing is the following:
In my LTspice netlist I ...
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