All Questions
Tagged with verification system-verilog
29
questions
2
votes
2
answers
38
views
The quality of testbenches with UVM testing
This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied.
So I come from a hardware engineering background, as I was discussing how ...
- 21
1
vote
1
answer
71
views
How to connect multiple TLM ports to UVM Sequencer?
There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
- 21
1
vote
2
answers
95
views
How to use "question mark" in start method of UVM?
I am trying to modify the existing code using the start() method in UVM.
Basic code is below:
...
- 619
2
votes
1
answer
730
views
Error while trying to bind SystemVerilog module with properties module
I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this:
...
1
vote
3
answers
497
views
Problem overridding parametrized UVM objects
In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence '...
1
vote
1
answer
944
views
Verification of asynchronous FIFO
I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings.
The goal is to verify this design by using the Tb components, so no UVM at all. I ...
1
vote
1
answer
96
views
Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?
For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right ...
-2
votes
1
answer
2k
views
Sign Extension in Verilog [closed]
what is the difference between the following 3 sign extensions
...
- 99
0
votes
1
answer
127
views
Has the user's guide for the UVM-IEEE-2020 framework been published yet? [closed]
I was able to find the User's guide for the UVM-1.1 and UVM-1.2 frameworks, but I haven't been able to find the same document for UVM-IEEE-2020.
There are of course resources posted at the Accellera's ...
- 181
0
votes
1
answer
2k
views
Is it possible to access signals in a DUT from a testbench written in a different HDL?
I believe such a question has been asked in the past but this is more comprehensive.
VHDL provides "external name" where we use an alias in a testbench to access signals that exist down the ...
- 2,103
0
votes
1
answer
1k
views
How to randomize the seed-number in Modelsim?
In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number.
I was ...
1
vote
1
answer
140
views
Test bench when design is pipelined
I have a design with chained modules. Each of them is a pipelined design, so the output in each of them take more than 1 clock cycle. To perform the test bench, I have created so many registered ...
- 115
0
votes
1
answer
740
views
SystemVerilog Assertions syntax error unexpected |-> [closed]
I'm starting to use SVAs for formal verification.
I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?):
as I do ...
- 327
2
votes
2
answers
231
views
How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?
I would like to write the following in SVA (SystemVerilog Assertion) format.
signal a should never be 2 until it attains the value 1
How can we do that?
- 155
0
votes
1
answer
251
views
Generating unique values for multiple cyclic random variables
In the following code, I have 2 cyclic random variables in a class. One (an enumerated type) takes 3 possible values, and the other takes 288 possible values (due to a constraint).
So, I expect to get ...