Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?

Question

For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right now is to realize a testbench in SV, creating all those components, for an Asynchronous FIFO, which you can find at the following link:

http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf

I know when it comes to realize a testbench in Verilog for a design, I should only focus on the top_level of the design, even if there are multiple modules instantiated inside. But, since now I need to realize the Transaction class, the Scoreboard, etc., I would like to be sure on what I need to focus.

Answer 1

Yes, for a design this small, you should focus on the top-level of the design, not the submodules.

Referring specifically to section "6.1 fifo1.v - FIFO top-level module" in the document, the top-level module (named fifo1) has a simple interfaces: input and output data busses, input controls and output status. The submodules are very simple: synchronizers, memory model and flag control logic. I don't think it is worth building models for each of those.

The focus should be to create a driver to send data into the FIFO. For this, you need a data transaction model, an interface and a generator to create the transactions. For the output, you need a monitor, an interface and a scoreboard to compare the input data to the output data.

If you eventually create a larger design that instantiates this FIFO module and includes other bulky design modules (like SPI/UART serial logic), then you would also create top-level models for these other design blocks.

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Se also: SystemVerilog testbench tutorial example