Questions tagged [verification]
Assurance of satisfiability of all the expected requirements in either software or hardware systems.
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How can a designer be sure to authorize only legit ICs? How is performed? How are cloned ICs prevented to be activated?
The above diagram is from the IC Activation (locking/unlocking) slide of Fighting against theft, cloning and counterfeiting of integrated circuits by Lilian Bossuet Associate Professor, CNRS Chaire of ...
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Is there a tool or method to list signals that have no reset in the HDL design for an FPGA?
I have to reuse an old VHDL draft design which was not fully verified and validated.
The code is huge - it takes around 30k slices to be implemented on an FPGA. I see that some signals are forgotten ...
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The quality of testbenches with UVM testing
This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied.
So I come from a hardware engineering background, as I was discussing how ...
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How to connect multiple TLM ports to UVM Sequencer?
There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
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ESD Workstations in Manufacturing Facility
I am a manufacturing engineer for a company that just inherited a large electrical build. I am struggling to find ESD information for multiple workbenches. This is my last resort so I am hoping you ...
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How to convert Sequential circuit into a combinational circuit?
My question in general asks how to transform a sequential circuit/FSM into a combinational circuit.
The reason why I'm asking is in SAT solving, we can use only combinational circuits. And so in ...
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Has the user's guide for the UVM-IEEE-2020 framework been published yet? [closed]
I was able to find the User's guide for the UVM-1.1 and UVM-1.2 frameworks, but I haven't been able to find the same document for UVM-IEEE-2020.
There are of course resources posted at the Accellera's ...
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Ascertaining that a BGA's decoupling capacitance is good enough
BGA parts often have a large number of power pins in the middle of the package. It is of course important to ensure that the power rail has been sufficiently capacitively decoupled. How can one go ...
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Transformer Design for a Series Resonant Converter
I am determining the Area-Product of the core required for a transformer to be used within a series resonant converter. The specifications are as follows:
Switching frequency = 400 kHz
Primary ...
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Current values verification check without ammeter [closed]
Given the following circuit with my current directions (the ones I highlighted with red):
So \$ I = - 2 A, I' = -1.5 A, I_x = \frac{1}{2} A , I_y = -1.5A , V_x = -1.5 A \$
Is this valid?
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How to test a CPU watchdog on board?
The watchdog of an ATMEL ATXMega128 should have been enabled with fuses. It triggers a reset, if the timer was not reset within the configured time span.
I want to be sure, that it is enabled and ...
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Where should I instantiate the DUT object, in the testbench file or in the task?
I am making a testbench in Verilog where it will call different test cases from different modules: each module, one test case/task.
Where should I instantiate the DUT object, in the testbench file or ...
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How to use "question mark" in start method of UVM?
I am trying to modify the existing code using the start() method in UVM.
Basic code is below:
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Problem overridding parametrized UVM objects
In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence '...
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Error while trying to bind SystemVerilog module with properties module
I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this:
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