All Questions
Tagged with verification uvm
5
questions
2
votes
2
answers
38
views
The quality of testbenches with UVM testing
This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied.
So I come from a hardware engineering background, as I was discussing how ...
- 21
1
vote
1
answer
71
views
How to connect multiple TLM ports to UVM Sequencer?
There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
- 21
1
vote
2
answers
95
views
How to use "question mark" in start method of UVM?
I am trying to modify the existing code using the start() method in UVM.
Basic code is below:
...
- 619
1
vote
3
answers
497
views
Problem overridding parametrized UVM objects
In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence '...
0
votes
1
answer
127
views
Has the user's guide for the UVM-IEEE-2020 framework been published yet? [closed]
I was able to find the User's guide for the UVM-1.1 and UVM-1.2 frameworks, but I haven't been able to find the same document for UVM-IEEE-2020.
There are of course resources posted at the Accellera's ...
- 181