All Questions
Tagged with verification simulation
4
questions
1
vote
1
answer
71
views
How to connect multiple TLM ports to UVM Sequencer?
There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
- 21
1
vote
3
answers
497
views
Problem overridding parametrized UVM objects
In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence '...
2
votes
2
answers
88
views
Transaction randomization succeeds, yet values do not meet constraints
In the following code, I attempt to randomize the transaction which contains a dynamic array 'PhyRB', with the constraint that each element in the array is less than 'ResBlks' value. Please note that ...
1
vote
1
answer
504
views
Failed to randomize dynamic array using foreach in constraint
In the following code, I force a random variable 'ResBlks' with a value (setting its rand_mode to 0), then attempt to randomize the transaction:
...