All Questions
Tagged with verification vhdl
7
questions
0
votes
1
answer
2k
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Is it possible to access signals in a DUT from a testbench written in a different HDL?
I believe such a question has been asked in the past but this is more comprehensive.
VHDL provides "external name" where we use an alias in a testbench to access signals that exist down the ...
2
votes
1
answer
400
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Resources for learning Open Source VHDL Verification Methodology (OSVVM) [closed]
I am looking forward to learn Open Source VHDL Verification Methodology (OSVVM). In this regard, I wanted to know the following:
Can I use Xilinx ISE v10.1 and its in-built simulator for OSVVM based ...
2
votes
1
answer
110
views
Verifying custom Qsys component?
A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also.
These copies ...
0
votes
2
answers
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How to verify a VHDL I2C master?
Once an I2C master has been written, the next step is verification. Provided that a BFM for the slave does not exist, how should one go about doing this? Also seeing how I2C is open collector in ...
6
votes
2
answers
1k
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Is there a "standard" way to verify HDL of a state machine?
State machines are a pattern that is used very often in writing synchronous designs. They serve as the controllers in the design. So, is there a standard way to verify them if they are written using ...
3
votes
1
answer
221
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Modelsim - Weird verification problem with DDR and Xilinx UNISIM
I am doing verification of VHDL component using OVM and ran into serious problems. I have found that problem is in one specific component and created environment specifically for it. It's a RGMII to ...
16
votes
8
answers
17k
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What is the difference between testing and verification?
Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction.
To ...