Questions tagged [quartus]
Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).
225
questions
0
votes
1
answer
46
views
32 bit Multiplication synthesis in Quartus in VHDL on cyclone V FPGA
I encountered a strange behavior while simulating my ALU. I designed a 32-bit ALU in VHDL to perform addition, subtraction, multiplication, division, OR, AND, and XOR operations. During simulation, ...
- 13
0
votes
0
answers
12
views
What is the purpose of monitor BFMs in Quartus Prime Platform Designer Simulation models?
Here is screenshot from Quartus Prime Platform Designer showing the Verification Components.
I understand the master/slave and source/sink. I have used them in the past long ago. What I don't ...
- 12k
0
votes
0
answers
49
views
Quartus: too long compilation time problem - Stratix 10
I have a big design the suffering from very long compilation times,
The time is about 7hours to 8hours.
I would like to know if its normal according to the following details:
FPGA Device: Intel ...
- 549
1
vote
1
answer
60
views
(Verilog) Why $signed() and >>> operation cannot generate ASR when inside ?: operator in such case?
Here is the module, I want to use signext to determine whether it is ASR or LSR.
...
- 13
0
votes
0
answers
32
views
SDRAM connection to Nios2 on DE10-Nano
I am pretty new to fpga world and trying to do an image processing application using Nios2 processor on a DE10-Nano dev board for university and I'm using the platform designer from Quartus. The goal ...
- 1
0
votes
1
answer
48
views
Packaging synthesized design as netlist for use in future designs
I am attempting to create a synthesized netlist of an FSM to help decrease my synthesis time, but I've been unable to get Quartus to generate the correct output files or even find any resources on ...
- 61
0
votes
1
answer
198
views
How to properly constrain this hold time?
I am puzzled, can't get to any seemingly simple and, what's more important, solution looking correctly.
There's a main fast clock, fclk, and I divide it by 4, ...
- 7,120
2
votes
4
answers
2k
views
Is there any way to know how real discrete components are being connected to each other using logical gates?
Let's say we created some gates or something with VHDL. How can I convert that code into those diagrams that show how discrete components (such as transistors and resistors) are connected to each ...
- 31
2
votes
2
answers
151
views
Does this Verilog HDL code of a decoder look strange in any way?
I am wondering if it is ok to use output instead of wire for another output in Verilog coding (using Quartus for this). Just ...
1
vote
0
answers
206
views
How to obtain the counting of TTL pulses from an FPGA?
I'm currently working on a project in which I need to program an FPGA in order to connect it to a photon detector, that generates a TTL pulse when detecting a photon; I need to count this pulses, ...
- 11
1
vote
1
answer
136
views
How to make a waveform simulation in Quartus II from testbench module
I wrote a Verilog gate-level description and a testbench for these requirements. However, I don't know how to make a waveform simulation in Quartus II. How can I make the waveform simulation to get ...
- 401
0
votes
0
answers
143
views
SDC constraints at the module level
Must be simple question I can't find answer for.
I design Synposys design constraints file, and have a module, let's call it module1. A the top I connect it using
...
- 7,120
0
votes
1
answer
135
views
Choose the right strategy to divide two values [closed]
Info:
After getting some comments and already one answer, I decided to rewrite this question to better fit into this site.
I had a problem where I needed to downsize a 12 bit value to an 8 bit value. ...
- 209
0
votes
0
answers
87
views
Calculating timing constraings for interfacing with sdram
I want to set the set_input_delay and set_output_delay constraints for my design but I'm having trouble to find the values to calculate them.
My understanding so far:
To calculate the set_output_delay ...
- 209
0
votes
1
answer
51
views
Discrepancy between simulation results and RTL viewer in Quartus II 18.0 for my Verilog code
Here's the Verilog code for my UsedBeforeAssign module:
...
- 125