Questions tagged [asic]
An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.
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Why is static power more of a concern in smaller ASIC geometries than dynamic power?
I've read that the challenge of designing smaller ASIC geometry is the leakage current. I'm aware that dynamic power is the cause of most power consumption in CMOS, but leakage current is static power ...
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How is clock gating physically achieved inside an FPGA or ASIC?
It is bad idea to add logic gates in clock signal path. How is clock gating achieve in FPGA and ASIC designs and how does it prevent glitch in the output signal i.e the gated clock as it is enabled or ...
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Does the term micro-architecture have a meaning outside of microprocessors?
Wikipedia defines microarchitecture as follows:
In computer engineering, microarchitecture, also called computer
organization and sometimes abbreviated as µarch or uarch, is the way a
given ...
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How were custom chips designed in the days prior to the arrival of FPGAs as hardware emulation devices? [closed]
One of the applications of FPGAs is to model a computer system/chip/functionality on it prior to mass manufacturing the copies of finalized design. How was this done before FPGAs were used for this ...
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Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?
Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?
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What is the difference between "2 synchronize" and "metastability"?
As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below,
cross clock domain databus
But I came across about ...
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Synthesis rules for this procedural assignment (combinational circuit)
I am a noob asking elementary questions. So bear with me.
If I have the following code, what would the synthesis result be if it can be synthesized at all. will the synthesizer generate intermediate ...
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Synthesis output for the following verilog code
I have a somewhat stupid question as I am still a noob. So bear with me.
If I have the following statement in Verilog:
...
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behavior of a pipelined divider
Divider can be made combinational, which uses more logic gates..
Divider can be made sequential, the throughput may stay the same, i.e. use as many stages
as the width of the dividend (assuming width ...
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule
I have an issue in timing slack got from Design Compiler (DC.)
One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
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Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?
There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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How to Implement Relational Operation using TCAM?
Can we implement relational operations (<, > , >=, <= ) using TCAM? Even if they are possible to implement, are TCAMs used for relational operations in real life? What are the pros and ...
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ASIC gate count estimation and SRAM vs flip-flops
I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration.
Below is what I found out. Please feel free to correct, comment, expand.
Logic gates
Two ...
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What is the proper way to reset an output signal back to zero on the next clock edge?
Occasionally writing some FPGA-targeted Verilog code at my job, I often need to drive output signals high during one clock cycle exactly. Sometimes I use the following “trick“ to achieve this (let me ...
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What ASIC/MCU is in my keyboard?
I disassembled my unbranded USB keyboard to find out what ASIC/encoder/MCU is inside. The chip is (as expected) covered, like the following example:
How to find out which chip is underneath?
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