Questions tagged [verification]
Assurance of satisfiability of all the expected requirements in either software or hardware systems.
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How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?
I would like to write the following in SVA (SystemVerilog Assertion) format.
signal a should never be 2 until it attains the value 1
How can we do that?
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Generating unique values for multiple cyclic random variables
In the following code, I have 2 cyclic random variables in a class. One (an enumerated type) takes 3 possible values, and the other takes 288 possible values (due to a constraint).
So, I expect to get ...
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Transaction randomization succeeds, yet values do not meet constraints
In the following code, I attempt to randomize the transaction which contains a dynamic array 'PhyRB', with the constraint that each element in the array is less than 'ResBlks' value. Please note that ...
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Failed to randomize dynamic array using foreach in constraint
In the following code, I force a random variable 'ResBlks' with a value (setting its rand_mode to 0), then attempt to randomize the transaction:
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Verifying custom Qsys component?
A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also.
These copies ...
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How to verify a VHDL I2C master?
Once an I2C master has been written, the next step is verification. Provided that a BFM for the slave does not exist, how should one go about doing this? Also seeing how I2C is open collector in ...
- 12k
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Best way to structure Verilog module to allow for simulation clocks
Quick question that I am likely missing an obvious solution for. I have a relatively simple Verilog design which I'll call taco, where the top-level design entity is taco_top (because I'm writing this ...
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What could be the output current rating of the following shunt regulator?
I am trying to solve the 2013 paper set by ISRO for electrical engineers. I wanted to verify if my answer to Question no 18 is correct.
So \$I_L\$ is being drawn out of the circuit shown. Since the ...
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Looking for a short range detection and identification
I am currently building a smart cat door. One of its functionalities is that it keeps the door locked until our cat comes close to it, then it unlocks the door.
I tried using RFID, the RC522 because ...
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How to test a CPU watchdog on board?
The watchdog of an ATMEL ATXMega128 should have been enabled with fuses. It triggers a reset, if the timer was not reset within the configured time span.
I want to be sure, that it is enabled and ...
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If constraints in SystemVerilog
I have a class of sequence item with rand variables:
class my_seq_item extends uvm_sequence_item;
rand bit a, b, c, d;
I want to generate a random bit for 'd' ...
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Fault modelling stuck at fault for combinational circuit
A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing?
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System Verilog Coverpoint Bin for everything else that is counted towards coverage calculations
Setting a bin to default grabs everything else in the coverpoint, but the default bin is ignored in coverage calcuations. Is there anything similar to default that I can use for syntax that will ...
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ASIC verification of a FIFO with "n" unique items
simulate this circuit – Schematic created using CircuitLab
I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" ...
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What is formal verification of hardware?
I read that testing and verification are different but in what way? I read that somebody writes theory to prove that the hardware is "correct" but how is that done? I tried reading Wikipedia and ...
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