Questions tagged [verification]
Assurance of satisfiability of all the expected requirements in either software or hardware systems.
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Circuit Testing, Verification & Certification Standards for Biomedical Devices
Please note: I would have posted this question on HealthIT.SE but they are apparently now closed for business, and I believe this site is the next most appropriate place to ask this. I believe this ...
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Modelsim - Weird verification problem with DDR and Xilinx UNISIM
I am doing verification of VHDL component using OVM and ran into serious problems. I have found that problem is in one specific component and created environment specifically for it. It's a RGMII to ...
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EMC testing vs. EMI testing
What is the difference between EMC testing (Electromagnetic compatibility) and EMI testing (Electromagnetic interference)
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Verifying a Meier Crossfeed Build
I've built a "Bass Enhanced Crossfeed" from a kit, which I believe is based on Meier's Crossfeed design.
I prototyped it first on a breadboard, forgot to ground the output jack because it wasn't ...
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Of what real, practical use is electronics certification?
I am brand new to EE/ECE and am aware that companies such as UL offer a gammit of services such as:
Circuit verification (they verify your schematic does what its supposed to do and doesn't have any ...
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Testing paradigms for consumer electronics [closed]
I am brand new to EE/ECE (my background is software) and I am curious about how real-world electronics testing takes place.
In software, there are many different types of tests that a piece of code ...
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Error Loading Design Unresolved Reference
DUT:
module ANDgate(a, b, c);
input a;
input b;
output c;
assign c = a & b;
endmodule
TESTBENCH: Without task
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Where should I instantiate the DUT object, in the testbench file or in the task?
I am making a testbench in Verilog where it will call different test cases from different modules: each module, one test case/task.
Where should I instantiate the DUT object, in the testbench file or ...
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What do the following terms mean for verification engineers?
When it comes to verification of digital circuits, what is the difference between the meaning of the following terms:
What is the difference between specification and requirement?
What is the ...
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How to convert Sequential circuit into a combinational circuit?
My question in general asks how to transform a sequential circuit/FSM into a combinational circuit.
The reason why I'm asking is in SAT solving, we can use only combinational circuits. And so in ...
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Running UVM example on MODELSIM - ALTERA 10.1d
I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool.
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What do the terms code coverage and functional coverage refer to when it comes to digital design verification
It seems that verifying a design is a more complex task than the actual design itself and takes a lot longer to carry out. We may even need to create testbench to very the original testbench that ...
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How to write testbench for digital circuits that output video/audio signal
As far as I have seen, a testbench will provide some stimulus to a DUT and the output shall be compared with expected values. This is one way to verify.
Many digial circuits however, may produce more ...
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What is the difference between testing and verification?
Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction.
To ...
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Specman UVM: What is the difference between write_reg { .field == 2;}; and write_reg_fields?
I'm working with vr_ad package for e. My question is:
What is the difference between 2 following macros for modifying registers (suppose ...
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