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Questions tagged [nmos]

A n-channel metal-oxide semiconductor (nMOS) transistor has n-type carriers in the channel. A positive voltage on the gate turns inverts the substrate (PWell) creating the channel and turning the device on. The term may also be used to describe logic circuits built around nMOS transistors.

10 votes
8 answers
20k views

Low Drain-Source MOSFET Leakage

I've been looking at the SM74611 Smart Bypass Diode from Texas Instruments and am very impressed with the reported reverse leakage current (0.3uA at 25C). Considering the device has a N-Channel FET, ...
TRISAbits's user avatar
  • 1,378
34 votes
6 answers
146k views

In an NMOS, does current flow from source to drain or vice-versa?

In an NMOS, does current flow from source to drain or vice-versa? This Wikipedia page is confusing me: http://en.wikipedia.org/wiki/MOSFET The above image confuses me. For the N-channel, it shows ...
PitaJ's user avatar
  • 495
10 votes
5 answers
876 views

MOSFET failure in a high power AC-DC SMPS buck converter

I've made a AC-DC step down buck converter that converts 220 VAC to a variable 45 to 70 VDC at 5 to 10 A to charge a Li-Ion battery. I'm currently using ESP32 to drive a MOSFET driver (IR2110) to ...
Kevin's user avatar
  • 101
2 votes
2 answers
624 views

Why are the voltages the way they are in this transistor circuit?

This question is about what my book calls "transmission voltage" when an nmos is conncted to the power source, or a pmos is connected to ground. It has a hypothetical diagram ass shown: It ...
user394334's user avatar
0 votes
3 answers
236 views

Ambiguous symbol [duplicate]

Does anybody know what this symbol presents?
Fateme's user avatar
  • 338
28 votes
5 answers
4k views

Why old PMOS/NMOS logic needed multiple voltages?

Why does old PMOS/NMOS logic needed multiple voltages like +5, -5, and +12 volts? For example, old Intel 8080 processors, old DRAMs, e.t.c... I'm interested in the causes on the physical/layout ...
BarsMonster's user avatar
  • 3,219
14 votes
1 answer
8k views

Where are the depletion PMOS transistors?

In school, I was taught about PMOS and NMOS transistors, and about enhancement- and depletion-mode transistors. Here's the short version of what I understand: Enhancement means that the channel is ...
Stephen Collings's user avatar
5 votes
3 answers
578 views

Why is the transfer curve of a real MOS not perfectly quadratical?

I am a student and trying to understand the MOS transistor. So I have simulated the transfer curve of a MOS in Cadence and done a parametric sweep for WL (500n, 1000n). Here you can see the plot sqrt ...
Diemex's user avatar
  • 159
4 votes
1 answer
10k views

Can a N-channel MOSFET used as a highside switch

Hello I would like to add a high side switch for my circuit. Typically a physical switch can do this job but due to form factor restraints the switches that are rated for my application does not meet ...
Jake quin's user avatar
  • 1,944
3 votes
2 answers
398 views

NMOS high-side switch for buck converter

I am studying a buck converter using an NMOS for the high-side switching. The inverter is supplied by a 3.7 V battery and should power a 0.6 Ω load. The switching is done by a 100 kHz 0-3.3 V PWM ...
Severian's user avatar
2 votes
1 answer
417 views

NMOS saturation mode: why is there no channel?

I have a question about the saturation mode. The cross-section of an NMOS transistor in saturation mode is usually drawn like this: But it seems to me that there can be no current from source to ...
Ruben's user avatar
  • 170
2 votes
2 answers
766 views

Adjusting the rise and fall time of a gate driver

I have a hard time understanding the specifications of the UCC27511A-Q1 gate driver. I understand that for a period of 0.5 μs (2 MHz) it can supply a source current of 4 A and a sink current of 8 A. ...
i33SoDA's user avatar
  • 103
0 votes
1 answer
322 views

Simple NMOS simulation error. High voltage drop across the nmos when trying to make a MOSFET switch

I have this simple NMOS configuration in ltSpice. I would imagine that when V2 (Vg) goes high, Vds would go close to zero. But this simulation suggests that there is a very high voltage drop across ...
user P520's user avatar
  • 208
-1 votes
1 answer
85 views

Why we still observe leakage at gate when we ground source. drain, and body of NMOS?

Why we still observe leakage at gate when we ground source. drain, and body of NMOS? I think it has something to do with the gate oxide or capacitors but im not sure
Dan's user avatar
  • 1
33 votes
3 answers
10k views

Why would a Intel 8080 chip be destroyed if +12 V is connected before −5 V?

The Intel 8080 is a classic microprocessor released in 1974, fabricated using an enhancement-mode NMOS process, and shows various unique characteristics related to this process, such as the ...
比尔盖子's user avatar
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