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3 votes
1 answer
53 views

Voltage drop in NMOS inverter with enhancement load

In the enhancement load NMOS inverter, why is the voltage drop across M2 at least equal to Vth when VIN is low ? Is it because for M2 when VIN is low the voltages VGS = VDS, so VDS > VGS - Vth and ...
S214ky's user avatar
  • 63
0 votes
2 answers
242 views

What is the difference between an N-MOS FET and a tri-state buffer? [closed]

Is an N-MOS FET an equivalent of a tri-state buffer, where the source is the input, the gate is the enable, and the drain is the output?
Sny's user avatar
  • 109
1 vote
0 answers
89 views

Electric-lock control via NMOS matrix

Currently I am working on the design that allows to control 8x8 electric lock matrix via PIC16F877A. As in comments for somebody it was not obvious (btw it was mentioned) I am using 64 electric locks ...
Alioth's user avatar
  • 13
0 votes
1 answer
245 views

the inverter switching point

As we know the mobility of the "nmos" device is 3x greater than "pmos", and when we want to correct the switching point of an inverter for vdd/2 we usually change the W of the &...
Vahe Armenakyan's user avatar
-1 votes
2 answers
599 views

How do you go from gate level to transistor level?

Is there a good method to go from circuit at gate level or truth table to transistor level, other than trial and error? I have an example here to illustate what I am asking. We have the function \$X=(...
Speedyspeedboy's user avatar
1 vote
1 answer
615 views

PMOS/NMOS current direction and digital logic

What happens when the PMOS source is connected to negative Vcc (-Vcc). What I understand is that when the gate voltage is <=0 then the drain-source is connected. Normally I would expect current to ...
makala's user avatar
  • 17
0 votes
0 answers
76 views

NMOS Cascode Logic

I have following problem and I ask you ,if possible, any help to resolve it. Size the following circuit so that it achieves a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load ...
electronics2021's user avatar
1 vote
1 answer
159 views

Finding inverting vs non inverting functions

I'm learning CMOS systems and I'm struggling with the PMOS and NMOS part of it. So for example given F=minterms(m0,m1,m2...) I can do the kmap and get the function ...
Nonya Biness's user avatar
0 votes
2 answers
751 views

How does logic 1 get passed through an NMOS pass transistor?

I'm studying pass transistors. One thing I came across in several of the books is that when an NMOS has a logic state HIGH and the input terminal (the schematic below) is also HIGH, the output ...
Akib Ahmed Ishan's user avatar
0 votes
2 answers
278 views

Finding output voltage of a MOSFET using its datasheet

Given a supply voltage of 4800 mV to a resistor loaded NMOS inverter with a single Nmosfet (2N7002) and a 6 ohm resistor, what would be the output voltage when the input voltage is 3500 mV? How should ...
electrobuzz's user avatar
2 votes
2 answers
41 views

Is sum of currents equal to capacitor current for NMOS Inverter with Capacitor as Load?

I found this in my lecture notes and could not understand how drain current is equal to sum of load and (IL) capacitor currents (ICL) given in the figure for a NMOS Inverter with capacitor load. By ...
electrobuzz's user avatar
0 votes
4 answers
891 views

Details regarding PMOS and NMOS transistors used as gates

My lab instructor explained very briefly what transistors are and started by naming them NPN and PNP then switched to PMOS and NMOS and I (as well as my classmates) am very confused, I need someone to ...
Ralph Aouad's user avatar
1 vote
2 answers
3k views

Understanding the working of a NAND GATE using NMOS Transistors

I'm having incredible difficulties understanding how the "Switching Behaviour" (not sure if that's the correct English translation- in German it is "Schaltverhalten") for NMOS and PMOS transistors ...
Ski Mask's user avatar
  • 143
0 votes
2 answers
3k views

Deriving the NOT logic gate using PMOS logic

I recently started learning about Field Effect Transistors (FET's) and about the MOS circuit family. From my understanding NMOS is made from a p-type substrate and n-type source/drain, whereas the ...
Ski Mask's user avatar
  • 143
0 votes
2 answers
1k views

Output impedance of a logic inverter using an NMOS

I have drawn below an NMOS logic inverter and its equivalent circuit for HIGH state: Why is this gate said to have high output impedance at HIGH state? Is that because of the open switch or because ...
cm64's user avatar
  • 2,217

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