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0 votes
0 answers
76 views

NMOS Cascode Logic

I have following problem and I ask you ,if possible, any help to resolve it. Size the following circuit so that it achieves a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load ...
electronics2021's user avatar
0 votes
1 answer
66 views

MOS device sizes

Hello guys! I just want to ask what's the difference between the actual W/L and the W/L shown at the image below? I'm kind of confused. Thank you!
realner's user avatar
  • 31
33 votes
3 answers
10k views

Why would a Intel 8080 chip be destroyed if +12 V is connected before −5 V?

The Intel 8080 is a classic microprocessor released in 1974, fabricated using an enhancement-mode NMOS process, and shows various unique characteristics related to this process, such as the ...
比尔盖子's user avatar
  • 7,218
0 votes
3 answers
236 views

Ambiguous symbol [duplicate]

Does anybody know what this symbol presents?
Fateme's user avatar
  • 338
0 votes
1 answer
83 views

Deriving the Transistor Width for NOR

I'm an undergraduate electrical engineer and my universities notes are not the best, I have an assignment in which I do not want the answers to but the question has given me the oxide capacitance, ...
Adam Hughes's user avatar
0 votes
1 answer
806 views

How do you choose the exact width for PMOS/NMOS in your design?

I'm designing the following function: $$F = ((A'+B) \times (A+B'))'$$ This is the schematic: Now I know that in general PMOS width has to be 2-3 times that of NMOS width. But how do you decide ...
Osama Qarem's user avatar
1 vote
2 answers
499 views

PMOS carrying more current than NMOS?

I dont know what is happening here. Both PMOS and NMOS have W=100*270nm L=180nm Vgs=1.8v vds=1.8v while NMOS is carrying only 14.19mA current, How can PMOS carry 15.97mA for the same size and ...
the_star_lord's user avatar
1 vote
2 answers
1k views

Why MOS transconductance is not zero even when drain current is constant?

I am trying to plot transconductance \$ g_m \$ of the MOSFET below when \$ V_{gs} \$ varies from 0 to 1.8V. The schematic is below. The drain current is fixed to a constant DC value 1uA by a current ...
emnha's user avatar
  • 1,649
0 votes
1 answer
5k views

Bias common source diode connected load

To amplify small signal we need to bias M1 and M2 in saturation mode. Obviously, M2 is always in saturation because Vgd = 0. However, how should I bias M1 in saturation?
emnha's user avatar
  • 1,649