Skip to main content

All Questions

Tagged with
2 votes
1 answer
233 views

How can I take parameters from power NMOS and power PMOS transistors and translate these into LTspice simulations?

I am trying to simulate NMOS and PMOS power transistors in LTspice, but I keep getting error messages about the NMOS being duplicate. Some of the earlier LTspice file is here. I am trying to have a ...
Stephen Elliott's user avatar
1 vote
1 answer
153 views

Mosfet Linear Region LTspice simulation

I have a question regarding a mosfet simulation I am trying to perform. Here is the circuit in question. We can see that Vd=1kV , Vs=0V and Vg=10V(it is a pulsed source) Now to my understanding I ...
DRF's user avatar
  • 536
4 votes
1 answer
214 views

LTspice Half bridge current spikes

I simulated a half bridge with two NMOS and at every switching event a current spike up to 1.2 A in the voltage source V4 occurs. I used a resistor as load because with any inductive or capacitive ...
hanss's user avatar
  • 147
0 votes
2 answers
155 views

Vout NMOS CS amplifier LTspice simulation

I've been trying to create this 2 block cs amplifier for a 5V/V gain. The problem is that my Vout is saturated on both cycles, and I do not know why this is happening. The transistor used is NMOS ...
JuanPy 's user avatar
3 votes
1 answer
319 views

NMOS level 8 Ltspice model of 2SK4177

After downloading a model from https://www.onsemi.com/design/resources/technical-documentation?rpn=2SK4177, I deleted everything apart from what was between .MODEL and ), so I ended up with a xxx.txt ...
Hyp's user avatar
  • 877
0 votes
1 answer
996 views

How to do NMOS modeling analysis in Spice

Here is my circuit in Spice: I want to do a simple analysis of the NMOS like this: What kind of command should I use?
Mirage's user avatar
  • 1
0 votes
0 answers
653 views

Body effect on NMOS4 LTSpice simulation

I am trying to observe the effect of a negative voltage on the NMOS4 model in LTSpice. I have a DC sim running and a step parameter for the voltage. However the current curve (and threshold voltage) ...
Nic's user avatar
  • 1
0 votes
1 answer
335 views

Importing Third Party Models in LTSpice

I am trying to import the 2N3904 NMOS transistor in LTSpice but the program is not allowing me. I have pasted the model name in the spice schematic as shown below. The error message is : "cannot ...
Debbie's user avatar
  • 217
0 votes
1 answer
310 views

How to make NMOS resistance emulate a normal resistor?

I am trying to see the behaviour of an NMOS' resistance with gate-source voltage. This is my NMOS as voltage (Vgs) controlled resistor' schematic (I am doing DC sweep on V2 from 2V to 10V with step ...
Prasanjit Rath's user avatar
3 votes
1 answer
742 views

ALD1106/1107 transmission gate "off" state behaviour in LTSpice

I am making a transmission gate using ALD1106 NMOS and ALD1107 PMOS model files. For -5V (to NMOS and +5V to PMOS), with input 5V, the output should come 0 as the transistors would be in off state. ...
Prasanjit Rath's user avatar
1 vote
3 answers
111 views

How do i get to study the impact of body bias on NMOS threshold voltage using LTSpice?

I am new to LTSpice. I have tried a design in LTSpice for the above requirement. But I dont get the plot for different values of body bias Vsb.
Yadu Krishnan's user avatar
1 vote
1 answer
2k views

Incorporating ALD1106 SPICE model in LTspice

I'm trying to incorporate a SPICE model of an NMOS IC, the ALD1106. I've used it before in class, but it's been so long that I've forgotten how to incorporate the files into LTspice in order to ...
BestQualityVacuum's user avatar
4 votes
3 answers
13k views

Circuit with LTspice default NMOS model does not work as expected

I put together a circuit where I want to switch a load with a nMOSFET, but I get a load current that is unexpectedly low. I reduced the problem to this circuit: As can be seen the load current is ...
Sim Son's user avatar
  • 2,803
0 votes
1 answer
322 views

Simple NMOS simulation error. High voltage drop across the nmos when trying to make a MOSFET switch

I have this simple NMOS configuration in ltSpice. I would imagine that when V2 (Vg) goes high, Vds would go close to zero. But this simulation suggests that there is a very high voltage drop across ...
user P520's user avatar
  • 208
0 votes
2 answers
2k views

TSMC model for lt spice simulation [closed]

From where to download the tsmc model file for nmos(slow,fast,typical) and pmos (slow,fast,typical)?
Anand's user avatar
  • 43

15 30 50 per page