Questions tagged [cpu]
CPU is the abbreviation for central processing unit. Sometimes referred to simply as the central processor, but more commonly called processor
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Is it possible and faster to run an application on an unused CPU core?
Is it possible to move an application (or task) to another core to make it run faster and get all of that cores processing power?
The way I understand it is that in an operating system applications ...
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In software programming, would it be possible to have both CPU and GPU loads at 100%?
This is a general question on a subject I've found interesting as a gamer: CPU/GPU bottlenecks and programming. If I'm not mistaken, I've come to understand that both CPU and GPU calculate stuff, but ...
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Byte addressable vs bit addressable
Why are most computers byte addressable instead of bit addressable?
By B/b addressable I mean that processor can operate on level of single B/b.
Bit addressable advantages:
Booleans have size of ...
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Operation excution in terms of clock cycles
Typically for a single instrcution, 6 machine cycles are needed:
FETCH instruction
DECODE instruction
EVALUATE ADDRESS
fetch OPERANDS
EXECUTE oepration
STORE result
My concern is regarding the fifth ...
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What was the first mass-produced CPU to have an instruction for multiplication?
The CPU I am most familiar with is the Z80 which was first released in 1976. The most complicated mathematical single instructions it has are integer ADD, SUB and closely related instructions, such as ...
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Are there CPUs that perform this possible L1 cache write optimization?
When the CPU with an L1 cache does a write, what normally happens is that (assuming that the cache line that it is writing to is already in the L1 cache) the cache (in addition to updating the data) ...
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Handling exceptions in multiple-issue CPUs
From what I read, VLIWs execute instructions in bundles, i.e. the CPU loads a bundle of instructions and dispatches them all at once. This is possible because the compiler scheduled instructions in ...
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What could "move an instruction without a 16-bit bus" mean?
Spoiler alert! This question (and, possibly, answers) could contain spoilers regarding "Halt and Catch Fire" TV series.
Background
I'm a web deleloper and do not have a CS degreee, so my ...
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Which programming language is used to write a BIOS program?
As I understand, the BIOS code/bitstream that is held in the ROM should be generic (work alongside with multiple CPU types or ISAs). In addition, I saw mentioned on the web that it is possible to dump ...
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Cost of cache coherency/sharing data across multiple cores?
If I have two CPU cores, one is writing a particular cache line and the other core wishes to
Read
Write
the same cache line, what are the costs (in cycles) for doing so?
I am a little unsure ...
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Why do we have to wait for I/O?
It's always been known that Disk operations are slow and we know the reasons why they are slow.
So the question here is why do we have to wait for I/O or why is there such a thing as IOWait, etc.?
I ...
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Pre-calculate values or not on Raspberry Pi
Say that you want to rotate something 360 steps 100 times. You now have a choise to pre-calculate 360 sin and cos values once and then use the stored values 100 times, or you can calculate sin and cos ...
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What is a latency-bound and a memory-bound application in HPC?
I understand that in HPC hybrid systems, for instance a MIC architecture, main memory access is much slower than access to data in own cache or in the cache of another core.
I read that HPC MIC ...
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Relationship of common MCUs/CPUs to FPGA and ASIC
I'm trying to understand the relationship between "common" MCUs/CPUs such as Intel, AMD, PowerPC, AVR, ARM, etc. and FPGAs and ASICs.
Here is my understanding:
These commons MCUs/CPUs (again, Intel, ...
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Compiling and deploying a C program to an MCU running an RTOS
Please note: Even though I'm specifically talking about an RTOS called Embox here, and even though I'm talking about AVR/ARm, I think this question can be answered by anybody whose ever done a fair ...
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