All Questions
Tagged with cpu architecture
17
questions
-2
votes
1
answer
108
views
What are the CPU architectures for the most common general purpose devices (i.e., Android, Windows/Linux PC, RaspberryPi etc.)? [closed]
Wikipedia lists over 45 different Instruction Set Architectures.
I would bet that most of those are listed for legacy purposes, but I barely have any knowledge on the subject (I'm not even sure if ...
1
vote
4
answers
273
views
Is the maximum number of outstanding load instructions limited by the CPU architecture or the program?
I'm reviewing some lecture slides and had a question on the following slide :
Assumptions (8 clocks to transfer data) Up to 3 outstanding load requests.
The slide is illustrating that the number of ...
- 493
0
votes
2
answers
173
views
Complicated task scheduling architecture
So I want to make an application in which a user will hit an endpoint to save a job model to storage that includes some metadata to perform a long computation against which will be offloaded to a ...
- 101
-5
votes
2
answers
148
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Archival-quality future-proof pseudo-CPU architecture
Suppose we maintain a massive electronic library of texts/photos/videos etc., and want to ensure that these files are readable indefinitely long in the future. [Update] one of the major problems with ...
-3
votes
3
answers
393
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ALU and register relations
Does the ALU have its own memory or registers where it stores input operands etc. or does it only use CPU registers (that aren't only specifically used for ALU tasks)?
- 117
-3
votes
1
answer
145
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How to anticipate a software future where ARM (potentially) replaces x86 in server and PCs? [closed]
With the introduction of Apple M1 processor, ARM has stood up to be a capable competitor and an alternative to x86 processors. We can foresee a future where ARM captures considerable market share of ...
- 113
-4
votes
1
answer
113
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Where on the 64bit memory of a PC would one byte end up?
I have a simple question I think.
A typical pc with ram has a 64bit databus between the cpu and ram. Let's say the ram starts at address 0, and I write i byte to address 0. Now my question is, would ...
user369697
0
votes
4
answers
1k
views
Does instruction length affect cycles per instruction?
ISAs define things like instruction lengths and the instructions themselves and there are some things that I do not understand.
Does the instruction length (the amount of bits) affect the amount of ...
- 295
2
votes
1
answer
2k
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What receives the output of the ALU?
I know that the Arithmetic Logic Unit (ALU of a processor performs arithmetic (and bitwise) operations and the result is stored as the ALU's output - but what component, device or software is actually ...
- 295
0
votes
0
answers
87
views
Cost of cache coherency/sharing data across multiple cores?
If I have two CPU cores, one is writing a particular cache line and the other core wishes to
Read
Write
the same cache line, what are the costs (in cycles) for doing so?
I am a little unsure ...
- 1,469
5
votes
2
answers
9k
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What is a latency-bound and a memory-bound application in HPC?
I understand that in HPC hybrid systems, for instance a MIC architecture, main memory access is much slower than access to data in own cache or in the cache of another core.
I read that HPC MIC ...
- 151
1
vote
0
answers
515
views
What parallelism happens in a vector processor?
From Tanebaum's Structured Computer Organization
A vector processor is very efficient at executing a sequence of
operations on pairs of data elements. All of the operations are
performed in a ...
- 5,485
2
votes
2
answers
3k
views
What does "issue or start an instruction" mean?
From Section 2.1.3 RISC vs CISC from Structured Computer Organization by Tanenbaum,
While the initial emphasis was on simple instructions that could be
executed quickly, it was soon realized ...
- 5,485
9
votes
1
answer
4k
views
Understanding memory update propagation in x86/x86-64 CPU L1/L2/L3 caches and RAM
I'm trying to understand in a general sense how L1/L2 (and now L3 caches) are updated and how the updates are propagated in a multi-core x86/x86-64 CPU.
Assuming a 4 core CPU and 2 pairs of L1/L2 ...
- 91
6
votes
1
answer
3k
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Developing a compiler for a self made CPU Architecture
Recently ive been consumed by creating my own simple CPU architecture that at some point could be easily implemented in hardware (No FPGA, but actual Logic Gate circuits). Naturally to fulfill this ...
- 171