All Questions
4
questions
3
votes
4
answers
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How to align on both word size and cache lines in x86
From what it sounds like, a 64 bit processor means aligning to 64 bits, which means if you have unicode utf-8 stored in there, each 8-bit chunk would take up 64 bits of space. That doesn't really make ...
- 2,615
11
votes
4
answers
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Are there CPUs that perform this possible L1 cache write optimization?
When the CPU with an L1 cache does a write, what normally happens is that (assuming that the cache line that it is writing to is already in the L1 cache) the cache (in addition to updating the data) ...
- 221
9
votes
1
answer
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Understanding memory update propagation in x86/x86-64 CPU L1/L2/L3 caches and RAM
I'm trying to understand in a general sense how L1/L2 (and now L3 caches) are updated and how the updates are propagated in a multi-core x86/x86-64 CPU.
Assuming a 4 core CPU and 2 pairs of L1/L2 ...
- 91
0
votes
2
answers
839
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Intel Nehalem/SB/IB/Haswell CPUs, cache vs TLB
On the Nehalem+ architecture Intel CPUs what is the interaction between the L1 cache, L2 cache, L1 DTLB and L2 DTLB? On all the images I have found there isnt a clear explanation whether the CPU looks ...
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