All Questions
24
questions
1
vote
4
answers
273
views
Is the maximum number of outstanding load instructions limited by the CPU architecture or the program?
I'm reviewing some lecture slides and had a question on the following slide :
Assumptions (8 clocks to transfer data) Up to 3 outstanding load requests.
The slide is illustrating that the number of ...
- 493
1
vote
3
answers
546
views
Memory on multiple cores versus 1 core
I am running a program that, among other things, does some matrix multiplications, singular value decompositions and accessing matrix subsets on a very large data set (these are the lines of code that ...
- 19
1
vote
4
answers
2k
views
Memory Alignment
I want to make sure I understand the concept referred to by alignment:
Is it just a way of making sure that you never have a non-integer number of words? The wikipedia page says in order for an access ...
- 19
1
vote
3
answers
2k
views
How do binary numbers interact with the CPU and cause some action to take place? [duplicate]
EDIT: Perhaps what I am misunderstanding is that when it is said that the code we type gets turned into machine code of 0s and 1s. If these 0s and 1s are the abstracted representation of their ...
- 31
-4
votes
1
answer
113
views
Where on the 64bit memory of a PC would one byte end up?
I have a simple question I think.
A typical pc with ram has a 64bit databus between the cpu and ram. Let's say the ram starts at address 0, and I write i byte to address 0. Now my question is, would ...
user369697
3
votes
7
answers
3k
views
Is it possible to update exactly 1 byte in RAM?
For example I have a static C++ array {'d', 'o', 'c', 's'}. And I have x86 architecture, with 32-bits length words.
I want to replace letter c with g. As far as I understand, when we make a read ...
- 165
-2
votes
1
answer
701
views
Does accessing RAM from 2 threads double access time (synchronous access)?
As in topic.
If i want to access RAM from 2 different threads, completly different cells in memory, do they queue and are sent asynchronously or queue?
Lets say accessing memory from one thread (...
0
votes
2
answers
206
views
How did old OSs create or expand a segment in memory without issues?
On an 8086 CPU before the flat memory model had been adopted, when the OS wanted to create a new segment for a process, how did it know what virtual memory ranges were already covered by existing ...
- 141
3
votes
4
answers
4k
views
How to align on both word size and cache lines in x86
From what it sounds like, a 64 bit processor means aligning to 64 bits, which means if you have unicode utf-8 stored in there, each 8-bit chunk would take up 64 bits of space. That doesn't really make ...
- 2,615
7
votes
3
answers
7k
views
What does "address space" means when talking about IO devices?
The following quote is from this page:
While some CPU manufacturers implement a single address space in their
chips, others decided that peripheral devices are different from
memory and, ...
- 2,039
2
votes
1
answer
273
views
What does "data bus control" mean?
This video mentions the following:
What does it mean for the DMA controller to be granted the data bus control, does that mean the CPU cannot use the bus to access memory and IO devices until the DMA ...
- 2,039
0
votes
4
answers
1k
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When it is worth it to spend RAM for computational speed? [closed]
I am developing data analytics algorithms that are supposed to process large amounts of data.
Thus I am aiming to develop my mathematics already in such a way that it is possible to distribute the ...
- 307
2
votes
3
answers
3k
views
Source of loading value to the register or memory location
When we load a register or memory location with a value (e.g. MVI 3A or MVI 53), what initializes register or memory location with that specific value? It is the CPU who performs the initialization, ...
- 293
1
vote
3
answers
260
views
Pre-calculate values or not on Raspberry Pi
Say that you want to rotate something 360 steps 100 times. You now have a choise to pre-calculate 360 sin and cos values once and then use the stored values 100 times, or you can calculate sin and cos ...
- 227
5
votes
2
answers
9k
views
What is a latency-bound and a memory-bound application in HPC?
I understand that in HPC hybrid systems, for instance a MIC architecture, main memory access is much slower than access to data in own cache or in the cache of another core.
I read that HPC MIC ...
- 151