All Questions
11
questions
1
vote
1
answer
96
views
Can we reliably use unaligned scalars on contemporary hardware?
Processors have come a long way in their handling of unaligned data - from crashing at the very notion of it, through suffering severe penalties, all the way to having almost no impact.
I suppose it ...
- 723
-2
votes
2
answers
3k
views
How are electrons moved in processors/CPU? [duplicate]
During our class, he posed the question 'How are electrons moved by code' for our own reflection, the question seems to be vague but I assumed how are electrons moved in a processor/CPU since we were ...
- 23
7
votes
3
answers
7k
views
What does "address space" means when talking about IO devices?
The following quote is from this page:
While some CPU manufacturers implement a single address space in their
chips, others decided that peripheral devices are different from
memory and, ...
- 2,039
2
votes
1
answer
273
views
What does "data bus control" mean?
This video mentions the following:
What does it mean for the DMA controller to be granted the data bus control, does that mean the CPU cannot use the bus to access memory and IO devices until the DMA ...
- 2,039
73
votes
3
answers
65k
views
How does a single thread run on multiple cores?
I am trying to understand, at a high-level, how single threads run across multiple cores. Below is my best understanding. I do not believe it is correct though.
Based on my reading of Hyper-threading,...
- 1,550
3
votes
4
answers
676
views
Is it possible for a computer system to have constant/zero CPU load?
For example, a simple program in a simulated environment that waits for user input seems to be doing no work, so I guess it uses CPU only for the time.
I'd like to know if computer systems (that don'...
- 39
2
votes
2
answers
3k
views
Hardware accelerated text processing
Graphics processing units (GPUs) are very common and allow for efficient, parallel processing of floating point numbers.
PPUs (Physics Processing Units) used to be a buzzword several years ago but ...
- 1,353
19
votes
2
answers
22k
views
How long is a typical modern microprocessor pipeline?
I learnt some about pipelining but those were 4-stage and 5-stage and I think that modern pipelining typical is much longer and more complicated in practice. How long are typical pipelines and how ...
- 8,058
2
votes
1
answer
2k
views
Can we illustrate a CPU pipeline with a UML sequence diagram?
I study multicore pipelining and the diagrams are not UML sequence diagrams for instance
Why not remake this diagram like an UML sequence diagram, would not that be more clear so that we can see ...
- 8,058
32
votes
1
answer
1k
views
Performance of single-assignment ADT oriented code on modern CPUs
Working in immutable data with single assignments has the obvious effect of requiring more memory, one would presume, because you're constantly creating new values (though compilers under the covers ...
- 16.1k
26
votes
3
answers
25k
views
Why are there separate L1 caches for data and instructions?
Just went over some slides and noticed that the L1 cache (at least on Intel CPUs) distinguishes between data and instruction cache, I would like to know why this is..
- 556