All Questions
Tagged with cpu computer-architecture
13
questions
-2
votes
1
answer
108
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What are the CPU architectures for the most common general purpose devices (i.e., Android, Windows/Linux PC, RaspberryPi etc.)? [closed]
Wikipedia lists over 45 different Instruction Set Architectures.
I would bet that most of those are listed for legacy purposes, but I barely have any knowledge on the subject (I'm not even sure if ...
2
votes
0
answers
140
views
Branch Prediction: How does a correlative branch predictor select from the global history?
I am trying to understand how branch prediction works, specifically with regards to correlative branch prediction. I understand that in an (m, n) branch predictor, there are m branch predictors, with ...
- 129
2
votes
1
answer
273
views
What does "data bus control" mean?
This video mentions the following:
What does it mean for the DMA controller to be granted the data bus control, does that mean the CPU cannot use the bus to access memory and IO devices until the DMA ...
- 2,039
3
votes
4
answers
20k
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The difference between accumulator-based and register-based CPU architecture?
I don't understand the difference between an accumulator-based CPU architecture and a register-based CPU architecture. I know x86 is register-based but it has an accumulator-like register. I only ever ...
- 149
0
votes
1
answer
384
views
How is the data path controlled between ALU and registers?
On some machines the operation of data path between ALU and registers is controlled by microprogram . On some machines , it is controlled by
hardware .On machines with software control of the data ...
- 3
4
votes
4
answers
7k
views
Byte addressable vs bit addressable
Why are most computers byte addressable instead of bit addressable?
By B/b addressable I mean that processor can operate on level of single B/b.
Bit addressable advantages:
Booleans have size of ...
- 223
1
vote
3
answers
2k
views
Operation excution in terms of clock cycles
Typically for a single instrcution, 6 machine cycles are needed:
FETCH instruction
DECODE instruction
EVALUATE ADDRESS
fetch OPERANDS
EXECUTE oepration
STORE result
My concern is regarding the fifth ...
- 147
1
vote
1
answer
553
views
Relationship of common MCUs/CPUs to FPGA and ASIC
I'm trying to understand the relationship between "common" MCUs/CPUs such as Intel, AMD, PowerPC, AVR, ARM, etc. and FPGAs and ASICs.
Here is my understanding:
These commons MCUs/CPUs (again, Intel, ...
- 4,890
19
votes
2
answers
22k
views
How long is a typical modern microprocessor pipeline?
I learnt some about pipelining but those were 4-stage and 5-stage and I think that modern pipelining typical is much longer and more complicated in practice. How long are typical pipelines and how ...
- 8,058
2
votes
1
answer
2k
views
Can we illustrate a CPU pipeline with a UML sequence diagram?
I study multicore pipelining and the diagrams are not UML sequence diagrams for instance
Why not remake this diagram like an UML sequence diagram, would not that be more clear so that we can see ...
- 8,058
4
votes
2
answers
719
views
Is there genetic relationship between ARM and PDP-11 architectures?
Reading about ARM architecture I found many similarities to PDP-11 architecture which did not exist between ARM and x86.
For example,
General-purpose registers named Rx compared to AX, BX,... for x86
...
- 141
0
votes
3
answers
4k
views
Instruction vs data cache usage
Say I've got a cache memory where instruction and data have different cache memories ("Harvard architecture"). Which cache, instruction or data, is used most often? I mean "most often" as in time, not ...
- 8,058
2
votes
3
answers
1k
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Computers that operate exclusively on boolean algebra
I was wondering if there are any computers that operate exclusively on boolean operations. For example, no add, sub, mult, or div in the instruction set (although these could be emulated with the ...
- 211