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Questions tagged [packages]

In electronics packages refer to the physical encapsulation of a device. Most package names are standardized, so for example a TO-92 package will have similar dimensions and pin spacing between manufacturers so the same PCB footprint may be used. Be aware however many packages have subtle variations, for example TO-206AA, TO-206AB and TO-206AC.

1 vote
1 answer
176 views

Clarification of 'case' in junction to case thermal resistance

Junction to case thermal resistance (Rjc) is a key parameter when characterizing a package. It can be expressed as the temperature difference between the two locations over the heat dissipation. I am ...
FlakR's user avatar
  • 749
11 votes
3 answers
2k views

What does the 'junction' of a silicon semiconductor look like in real-life?

The P-N junction is a small area within a package where heating is most prominent. Junction temperature is a key parameter we try to track when operating a diode or a transistor. I am wondering what ...
FlakR's user avatar
  • 749
10 votes
2 answers
1k views

What does "end stackable" package mean for a MOSFET?

What is the manufacturer trying to say when they say "end stackable" here? They don't seriously mean vertically stacking the DIPs on top of each other in a tower and soldering the leads do ...
DKNguyen's user avatar
  • 56.9k
1 vote
3 answers
160 views

Space-grade flat package SMT

I wonder about space-grade ICs in flat packages. Space-grade flat package ICs have very long leads compared to the commercial versions. If I use a flat package IC on my CubeSAT board, can I modify the ...
mark-r6's user avatar
  • 15
2 votes
1 answer
787 views

What are wettable flanks in semiconductor packages?

What are wettable flanks? Is there any difference between packages with wettable flanks and other leadless packages? Can we say the package given above has wettable flanks?
Karthick selva's user avatar
2 votes
4 answers
374 views

Why do some transistor packages have multiple leads for the emitter?

I want to use a BJT transistor (edit: BFU768F, https://www.nxp.com/docs/en/data-sheet/BFU768F.pdf) that looks like this: I think I get why lead 1 is bigger than the rest. It's because both collector ...
Max's user avatar
  • 21
1 vote
4 answers
112 views

I don't know what this dimension means for a diode package drawing

I came across this case number and dimension for a diode, a D1NK60, that I would like to use: AX057: 3.0 × φ 2.6(mm) The data sheet is here (document page 31, PDF page 18). I don't know what phi ...
Otto Hunt's user avatar
  • 149
-1 votes
1 answer
109 views

Grid size for package creation in Eagle

I am creating a package for the first time, using Eagle for the first time. I took measurements of the component and these are the dimensions from the center: How exactly can I achieve these ...
user1584421's user avatar
  • 1,369
6 votes
3 answers
995 views

How is the CQFP64 package supposed to be soldered?

I am currently designing a PCB containing an ATmegaS128 with the CQFP64 package (see picture below and page 460 of its datasheet), but I do not know how it can be soldered. Can the golden frame and ...
charon25's user avatar
  • 351
0 votes
1 answer
93 views

How to ship LQFP 48 chips?

I have a bunch of STM MCUs (LQFP48 package) in hard plastic trays. I need to mail small quantities of them but it is impractical to cut up the trays. Looking for any suggestions on how to properly ...
user3191192's user avatar
0 votes
1 answer
710 views

What are the CRYSTAL package types?

Or, you can point me in the right direction :) I've found HC49 and variants, but no explanation of what the standard is or what the differences are between the different codes [ex. HC49/US, HC49/S, ...
MIMI-DISCONNECTOR's user avatar
3 votes
2 answers
704 views

Can a CPU heatsink be used to cool a TO-3P or a TO-220?

I want to know if my thermal design is appropriate for dissipating 72W of heat while keeping the junction temperature below 150 °C (I am trying to cool an SFH154 that comes in a TO-3P package). My ...
A.H.Z's user avatar
  • 633
1 vote
0 answers
54 views

Has any implementation succeeded to have shared key inside chipset and protect it from exploits?

Since there is a lot of demonstration like using SEM (Scanning Electron Microscope) to read bits from ROM through the scanned image of chipset, is there any implementation that has managed to succeed ...
hurryman2212's user avatar
3 votes
1 answer
83 views

Missing row 'I' in package numbering convention: why?

So, I recently discovered a quite painful mistake in my PCB regarding the PGA socket numbering. I have used a row numbered I in my footprint, while the package has ...
mxt3's user avatar
  • 161
0 votes
1 answer
207 views

UDFN Package, exposed thermal pad - to ground?

So I've got a design in which I would like to use the AT25SF321B-MHB-T chip by Dialog Semiconductors, but its datasheet does not mention whether the exposed thermal pad should be connected to ground ...
Cyborgium's user avatar
  • 159

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