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1 vote
1 answer
165 views

Package and footprint - Are they correct

In this device, on page 208, the page has the Package outline drawing. 8-pin package. SOIC. "8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ)" I want the footprint of this ...
Freshman's user avatar
-1 votes
1 answer
109 views

Grid size for package creation in Eagle

I am creating a package for the first time, using Eagle for the first time. I took measurements of the component and these are the dimensions from the center: How exactly can I achieve these ...
user1584421's user avatar
  • 1,369
5 votes
2 answers
627 views

Why do some exposed pads have small tabs, and does my PCB footprint need them?

I've noticed a few component packages now that have small "tabs" on the sides of their exposed pad (thermal pad). One example is the Analog Devices ADM7154 LDO: Note the 0.356 x 0.457 mm ...
TypeIA's user avatar
  • 2,426
-1 votes
1 answer
53 views

Three different dimensions shown in package drawing, what do they mean?

I have an IC that uses this package from analog devices: https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_8_5.pdf. Most of the dimensions are shown in three numbers: I ...
AnB's user avatar
  • 39
0 votes
1 answer
70 views

How to identify pin 1 from mechanical design

Looking at 10142048 datasheet from TE I'm not sure how to identify pin 1 from top side. At page 9 there are the pin assignments from bottom side only. Now, I guess: ...
Mark's user avatar
  • 1,235
0 votes
0 answers
99 views

Reducing Thermal Pad Size Below Official Footprint - Can It Create Manufacturability Problems?

I'm using a DP83867 Ethernet chip by Texas Instruments in an S-PQFP-G64, 10 x 10 mm package, the mechanical dimension and its recommended footprint are shown at the end of the question. As shown, the ...
比尔盖子's user avatar
  • 7,218
1 vote
1 answer
375 views

Why have the same chip in the same package, but with a different number of pins?

STMicroelectronics offers the following two accelerometer chips. The LIS2DW in a 14 pin LGA package The LIS2DW12 in a 12 pin LGA package These two chips are functionally equivalent and have the same ...
ajheck's user avatar
  • 113
0 votes
1 answer
488 views

Analog Devices `SOIC_N` and `MSOP_N` Recommended Footprints

I do not know if this is on topic, but which are the recommended footprints dimensions (or a reference document) for the SOIC_N and ...
Brethlosze's user avatar
  • 1,427
0 votes
0 answers
385 views

How to update a packaging made in an original design to the one previously used in another design Proteus

I'm working in a design in Proteus where I'm making a multi-board design. I've made a previous design where I've made a PCB model of an ESP8266-ESP01 but initially I was mistaken with the pin ...
vram's user avatar
  • 158
13 votes
2 answers
1k views

‘One for all’ standardized land pattern v.s. specified land pattern in datasheet

I’ve designed lot of ‘simple’ PCBs for hobby and proof-of-concept purposes, but never for (mass)manufacturing. In order to do so in the future, and further expanding my design skills and knowledge, I’...
Julien Roels's user avatar
1 vote
1 answer
850 views

Different footprints for different surface mount Resistor packaging?

When using the same surface mount package size (0402) for all my resistors on a board, but using resistors from different manufacturers or with different resistance values, should I create a different ...
Francis Poirier's user avatar
1 vote
2 answers
472 views

SO-8FL Package Footprint Eagle PCB

I am making a PCB with a component that is of the package SO-8FL. The component is n-channel MOSFET NVMFS4C03N by ON Semiconductor and the datasheet is here. I started to make the package in Eagle, ...
Blake's user avatar
  • 13
3 votes
2 answers
3k views

How to properly define BGA footprint in Eagle?

This question is somewhat relevant to this one. However I am sure it well deserves to be separate. I created a custom device/symbol/footprint for an ARM MCU. However I am doubtful whether I created a ...
Alexey Kamenskiy's user avatar
2 votes
2 answers
928 views

Cost effect of different component packages during PCB assembly

We are looking at starting PCB design in house, up until now we have outsource design and manufacture. This means that we have yet to see the real cost of the PCB, components and assembly as discrete ...
Puffafish's user avatar
  • 4,146
1 vote
0 answers
57 views

placing hermetical packages on PCB and soldering

I stumbled upon some hermetically enclosed packaged - Link. The package has a small bulge/projection on the bottom. This makes the package leads basically float without contact with the PCB. How do we ...
Board-Man's user avatar
  • 1,929

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