All Questions
10
questions
1
vote
0
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50
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MOSFET SOA: Isn't the package current limit-line ambient temperature dependent?
Ref 1 says "The package limit-line will not change in case application conditions such as ambient
temperature vary"
As explained in Ref2, this limit is due to bond wire heating/melting.
If ...
- 3,032
0
votes
1
answer
54
views
What does the interface between lead(s) and the silicon chip look like inside a semiconductor package?
For a leaded semiconductor, like a diode or a transistor, one of the leads is usually the same piece of metal as the copper pad/heat spreader on the back, which is also shorted to one of the junctions ...
- 749
1
vote
1
answer
120
views
What is the type of material used for the casing of semiconductors?
I am trying to build some thermal models for leaded and surface-mount diodes and transistors.
Below is a picture of the TO-220 outline I got from the internet. What kind of material is the black part ...
- 749
1
vote
1
answer
176
views
Clarification of 'case' in junction to case thermal resistance
Junction to case thermal resistance (Rjc) is a key parameter when characterizing a package. It can be expressed as the temperature difference between the two locations over the heat dissipation.
I am ...
- 749
3
votes
2
answers
703
views
Can a CPU heatsink be used to cool a TO-3P or a TO-220?
I want to know if my thermal design is appropriate for dissipating 72W of heat while keeping the junction temperature below 150 °C (I am trying to cool an SFH154 that comes in a TO-3P package). My ...
- 633
0
votes
1
answer
207
views
UDFN Package, exposed thermal pad - to ground?
So I've got a design in which I would like to use the AT25SF321B-MHB-T chip by Dialog Semiconductors, but its datasheet does not mention whether the exposed thermal pad should be connected to ground ...
- 159
5
votes
3
answers
742
views
Very high temperature (>500C) IC packages
I was looking for IC packages where I can mount a small wafer (3mmx3mm) wire bond to the leads of the package and conduct operation at 500C. I have contacted couple of companies which do ceramic IC ...
-2
votes
1
answer
67
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Resources for finding thermal impedances for common IC packages
I'm just looking for some extra resources for thermal impedances of JEDEC standardized packages. I've already found one such article posted by JRC, https://www.njr.com/semicon/package/thermal.html , ...
1
vote
2
answers
1k
views
MOSfet thermal design: die-to-package always DRAIN?
All the MOSfet chips seem to have substrate = DRAIN, which means that the heat-dissipation path goes that way. It is assumed that the package DRAIN pin would conduct away most heat from the package to ...
- 26.7k
2
votes
4
answers
853
views
Proper board layout for high power SMT FETs
I came across an SMT FET (IPT015N10N5ATMA1) that has an output of 300Amps in a rather small form factor. Are thermal vias enough to get heat away from the 8-PowerSFN package? Or would something like ...
- 286