Questions tagged [zynq]
Zynq is a range of programmable SoCs from Xilinx, that integrate an ARM-based processor and an FPGA fabric.
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Choosing DDR3 for Zynq-7000 (XC7Z010-1CLG400I)
Looking at the AC characteristics of the Zynq-7000 it is said that the maximum data rate of the -1 speed grade is 800Mbit/s (it is also specifically mentioned that the clock frequency for data ...
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ZYNQ FPGA Develope tool chain on mac
I have an Macbook m3, and a third party ZYNQ 7020 board. I understand that Xilinx doesn't support macos platform at this stage. but I wondering if anyone can show me an toolchain to develop PL and PS ...
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Simulating and verifying DDR3L clock
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I am working on a PCB that hosts a Zynq Ultrascale+ SoC and has 9 DDR3L SDRAMs (MT41K512M8DA) operating at 1866Mbps, and I have to verify the signal integrity of the DDR3L interface. I am ...
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What tool is required to implement data transfer between PS and PL of Zynq 7000 SoC?
I am new to embedded programming. I undetstand a little bit what Vivado and Petalinux does. But I would like to how exactly I can use Vivado and Petalinux to perform data transfer between ...
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DAC DDR Interface with Vivado and Zynq7000
i need to connect a dual-channel DAC (AD9117) to a Zynq 7000 FPGA. The DAC has a DDR Interface, on which the Data for Channel 1 is clocked on the rising edge and the data for channel 2 on the falling ...
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VHDL rising_edge on 1Hz GPS input
The FPGA project I am working on requires events within an FPGA to be triggered off a 1Hz PPS coming from a GPS module. I have sampled this pps and then tried implemented logic triggered by this ...
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How to use Zynq to program STM32 MCU?
I have a custom Zynq board. I need to use this board to program the STM32.
The binary of STM32 will be stored on the Zynq board. How can this be done?
I am assuming jtag/swd but not sure how to do it.
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Is it possible to use basic networking on an FPGA without an OS?
I need to set up networking (just a basic echo server) on an FPGA board (ZYNQ Ultrascale+) using only the PL side. The end goal is to DSP a large amount of data coming from a receiver through ethernet....
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Zynq PS_SRST pin is not connected in my design - can I still avoid locking the device down?
Unfortunately our board design is missing the PS_SRST pin connection on our Zynq XC7Z045 device - it is not connected (not pulled high or low). As a result the device is (apparently) entering lock ...
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vivado HLS or SDsoc for use openCV
I want to do an image processing by openCV on FPGA . But I do not know if I should use the SDsoc method or the vivadoHLS method. The size of the images I am going to process is large and I want to ...
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Power Consumption for DDR3L SDRAM IC's
Designing a board that will utilize some DDR3L memory for the first time and looking to gain some confidence in some steps I've assumed/taken so far.
I plan to use two 4Gb SDRAM IC's (MT41K256M16TW-...
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How many DDR memory chips can be connected to Zynq UltraScale+ MPSoC ZCU104
I have a question regarding Zynq UltraScale+ MPSoC: how many DDR RAMs can be connected to the ZU7EV device, including both PS and PL banks ?
Here is the link for TRM.
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JTAG ID to differentiate similar devices
Is there a reasonable way to identify different boards with the same parts through JTAG? I have a family of boards that all have the same Zynq CPU but various hardware configurations. I'd like to be ...
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Trying to use 5 registers in Xilinx's AXI Lite interface
I have an IP for Digilent's Zybo Z7-20 which segments the image. The segmentation is done based on histogram. The segmentation module takes 4 32-bit wide inputs which contain the threshold values. In ...
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Direct Access to Ethernet port via FPGA on Pynq-z2 board
I am using the pynq board for developing FPGA code for an application. For communication with the PC I am using the ethernet port given on the pynq board. By default the ethernet port is configured to ...
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