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Electrical Engineering
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zzzhhh
  • Member for 1 year, 4 months
  • Last seen more than 1 year ago
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1
Is there any chance to configure DDR3L SDRAM on Digilent Arty A7 FPGA development board to Dual Channel memory?
Mar 31, 2023
1
"ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources." in newest Vivado
Apr 5, 2023
0
Is there any chance to embed two DDR IP cores into FPGA so that I can implement dual-channel memory architecture?
Apr 1, 2023
0
"ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources." in newest Vivado
Apr 5, 2023
-1
Evaluate before delay, or delay before evaluate?
Apr 7, 2023
-1
"ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources." in newest Vivado
Apr 12, 2023
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/var/log/auth.log stops recording authentication errors