Questions tagged [instruction-set]
For questions regarding the instruction sets of microprocessors.
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What was the 6-bit length instruction(s) in the Intel iAPX 432?
The iAPX 432 was arguably the most complex processor architecture ever and a commercial failure for Intel. It was a stack machine with no visible general-purpose registers. It had hardware support ...
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Did any processor implement an integer square root instruction?
Has any processor ever implemented an integer square root instruction? Obviously, floating-point square root instructions are quite common, but I've never seen one specifically for integers.
One close ...
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What aspects of microprocessor ISAs have been patented?
A key objective of RISC-V was that every aspect of the ISA must be based on an expired patent. It was felt that this is the only truly reliable defense against patent lawsuits.
It is surprising that ...
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Why does the Z22 have a read-only shadow of the return address location?
For some context to this question see Raffzahn's excellent question and answer How were Zuse Z22 Instructions Encoded?.
The Z22 treats the first few locations of its address space in a particular way:...
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Original instruction set for the first ARM processor
I'm studying ISAs and would really like to see the very first ISA that Sophie Wilson chose/put together when designing the very first ARM CPU while at Acorn Computers around 1983 or so.
From what I ...
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IMPI Instruction set: is there any reference?
I've had an IBM 9404 B-10 for some time and I'm curious about its assembly language. I'm fully aware the AS lines were designed with portability in mind as much IBM didn't seem to provide assembly ...
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Would compare-and-branch have added an extra cycle on ARM-1?
The ARM-1 was an early RISC CPU, designed in 1986 (and even more typical of early RISC design constraints than the year would suggest, since Acorn didn't have the budget to pay for the latest process ...
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Why does the LGP-30 leave half its instruction word unused?
I am looking at the machine code for the LGP-30, which is found to have a very strange instruction word layout.
12 ignored bits
4 bits for the opcode
2 more ignored bits
12 bits for the operand, ...
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Is there a CPU ISA preferring a test for the value of one over testing for zero?
While discussing a question about the origin of Zero as value for the default exit code for success, I reflected if there is any Instruction Set Architecture or implementation thereof where testing a ...
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Carry handling during address generation on a 6502
I'm trying to learn a bit more about the internal workings of the 6502.
The manual says that the branch instructions do not affect the carry flag. However, my understanding is that some carry handling ...
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Null-terminated strings on the PDP-7?
I came across a post that states that Unix uses null-terminated strings, ASCIZ, because it was a feature of the PDP-7. This triggered my reading on the CIS instructions in the PDP-11, but these were ...
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What are the “building bricks” of ARM’s design that this magazine article is referring to?
I came across an early mention of the ARM in New Scientist of June 18, 1987:
https://books.google.ca/books?id=LvhAoKR-ixwC&pg=PA41
It has this statement:
They realised that many of the ...
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What motivated the weird boolean instruction repertoire of the PDP-11?
The PDP-11 has seven dyadic instructions (I'm not counting the byte/word varieties separately), which take a full six bits for each of its operands. That's twelve bits to specify the operands, and ...
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Why does the x86 not have an instruction to obtain its instruction pointer?
This has always confused me. Why can you not directly obtain the IP, and instead have to go through some odd assembly hoops such as calling a function whose only purpose is to push its own return ...
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What was the first CPU/FPU without a hardware square-rooter?
The first programmable, electronic, general-purpose digital computer, ENIAC had a "square rooter":
five of the accumulators were controlled by a special divider/square-rooter unit to ...
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