How do processor transistor counts keep increasing, without geometric scaling?

Question

Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "equivalent" and no longer relate to physical dimensions. However, the data showing transistor count suggests that this still follows the 'double every 2 years' trend.

How is this possible, if the transistors themselves are not scaling down at this rate?

Has the counting method changed to suit this? Is it for marketing? Or am I missing something in terms of design that continues to push this figure up?

Answer 1

For a given size chip area, the number of transistors on it continues to increase as the size of the transistor -the feature size - decreases. What that comment is implying is the node name, 5 nm for example, does not have a feature in the transistor, such as a gate width (drawn or actual), that is 5 nm long.

IEEE Spectrum had a good article about this very thing in one of last year's issues.

Answer 2

Chips are much larger laterally today. This allows placing more transistors into what qualifies as one chip. Growing sideways also helps keeping power density in check.

For example, large GPUs can be on the order of 600 mm² and consume 300 W, while chips from 20 years ago were closer to a third of this in both metrics.

Here is an insightful article linked by @BruceAbbott . It states:

[...], in the 25 years since the release of the Intel 80386, transistor area has shrunk by a factor of almost 4,000. [...] An analysis of commercial microprocessors, however, shows that transistor count has actually grown by a factor of 16,000. One simple reason why transistor growth has outpaced feature size is that processor dies have grown.

That article also shows that after 2005, the transistor density scaled even slower than the litho resolution, due to power density restrictions (around Figure 5).

Answer 3

I understand that scaling down and modern node names (7nm, 5nm etc) are now "equivalent" and no longer relate to physical dimensions.

You're misunderstanding what is meant by that. The names are not measurements of any specific dimension or parameter, but they are still roughly proportional to overall transistor area. More precisely, within a given manufacturer, whatever process they were selling 2 years ago has roughly half as many transistors per area. They may not call those exact nodes N and N/2 (since the names are arbitrary) but density scaling has still largely been maintained and probably will be for at least a few more years.

How is this possible, if the transistors themselves are not scaling down at this rate?

Transistors are scaling down at that rate.

Answer 4

1. The size of the semiconductor dies, or integrated circuits, have been increasing.
2. Companies are moving towards 3-D IC design.
3. Companies are moving towards wafer-scale computing or wafer-scale IC design, such as Cerebras Systems. See https://cerebras.net/. NVIDIA is exploring wafer-scale computing with TSMC. It is new because it has never been done before with large wafers, such as wafers with a diameter of 300 mm. This allows coarse-grain reconfigurable architecture for the wafer to have much for functional units to reconfigure and exploit. E.g., mapping a very large-scale deep learning network onto it. It haven't been done due to semiconductor manufacturing yield problems, due to very/ultra deep submicron and now nanoscale semiconductor manufacturing process technologies. But, TSMC gets away with it by connecting the isolated dies, which are normally isolated from each other to allow them to be separated from each other (slicing the wafer into dies). Here, TSMC just keeps the wafer intact, and use inter-die interconnects to connect the dies together. This integration of all the dies on a wafer provides much more opportunities to connect the functional blocks than packaged dies with much slower interconnects connecting them on boards. Wafer-scale computing enables all the dies to be connected without separating them via packages and inter-package interconnects. This is not an incremental innovation.

P/S: New transistors that can combine data storage and computation, or devices that perform other tasks (current regulation and retention of past behavior, such as memristors), allow logic gates and circuits to be redesigned with less transistors. Hence, we need not improve IC designs on various metrics, like performance/latency/delay, energy efficiency, and resource usage (number of logic cells/gates used or area of IC layout), by simply using semiconductor manufacturing process technologies that solely focus on improving transistor count.