All Questions
Tagged with semiconductors cmos
21
questions
1
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0
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40
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What is / how do I find the general ratios of all of the materials used in a cmos chip?
I am doing a life cycle assessment of a CMOS chip. But I am struggling a lot in finding the general ratios or quantities of the materials used in a chip, which is necessary for calculation of ...
- 11
0
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1
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99
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Process compatibility between a non-planar avalanche photodiode and planar CMOS at 0.130μm process technology node
I plan to integrate a non-planar P⁺⁺/i/P⁺/N⁺⁺ avalanche photodiode (APD) array with a peripheral control circuit (e.g., trans-impedance amplifier, analog-to-digital converter, and quenching circuit) ...
6
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1
answer
3k
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Why does higher temperature decrease NMOS threshold voltage?
The threshold voltage of a MOSFET decreases as temperature increases.
I don't understand this. Consider an n-type MOSFET that is fabricated in a p-doped silicon substrate. For a channel/inversion ...
- 3,145
0
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2
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210
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Could we use holes in an NMOS?
In an NMOS we have a p-substrate, and we use a positive voltage to attract negative charge "to the top". But could we have used negative charge to attract holes instead and gotten a "...
- 299
2
votes
1
answer
545
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Purpose of field implant in semiconductor manufacturing
I recently joined the semiconductor manufacturing industry.
In one of the process flows, I see a stage that has extra boron implantation step (called the field implant) in the P-WELL region.
I've ...
- 21
3
votes
4
answers
3k
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How do processor transistor counts keep increasing, without geometric scaling?
Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
- 31
0
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0
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253
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What does "field" in field oxide mean?
This is an excerpt from Design of Analog CMOS Integrated Circuits by Behzad Razavi. What does "field" in field oxide mean here, electric field?
- 240
3
votes
1
answer
896
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What exactly do the well taps in MOSFETs do and how?
Do they affect the flow of charge carriers or charge concentrations at all in the device? How so? Up to this point I've tried to visualize the effects that the various doped areas had on device ...
- 267
0
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0
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43
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Short Channel MOSFET model
I was reading on a book (Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits) that in a short channel model, since the phenomenon of drift speed saturation is very relevant, it is a ...
- 3,550
3
votes
5
answers
3k
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Why reverse connected MOSFET start to turn on at Vgs<Vth?
The circuit shown below is implemented using two AO3400 N-MOSFETs.
AO4300 datasheet here.
The right-hand MOSFET is connected with normal polarity (Vds is positive),
while the left-hand MOSFET is ...
- 93
0
votes
3
answers
667
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Mosfet Threshold Voltage
from MOS theory we know that, in case of a P substrate, a Gate-Bulk voltage higher than a certain threshold value creates an inversion layer, in this case made of negative charges. This is also ...
- 3,550
2
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4
answers
2k
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Why propagation delay is measured at 50% of the input and output waveform?
I didn't find the concept of propagation delay measured at a particular point on the waveform.
- 21
0
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1
answer
441
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Why does the current in MOSFET have a quadratic function (explain logically without using the integration method)?
The current equation relating Vds ,Vgs and Vt is already known to us ,but if there is any way we can find out how it varies quadratically without using the formulae?
- 21
6
votes
1
answer
163
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MOSFET switching on
I have a doubt. Consider an N-MOSFET: which is the voltage that can switch on it? The voltage between Gate and? Sometimes I read "between Gate and Bulk", sometimes "between Gate and Source", sometimes ...
- 3,550
2
votes
3
answers
824
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Latch-Up in CMOS-Devices
I recently read something about the latch-up effect in CMOS-Structures but I don't understand why are MOSFETs affected by this effect. I understand that high currents through the source-drain path ...
- 123
0
votes
1
answer
203
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Identifying the logic function of this specific MOS layout
I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C).
Can anyone confirm or correct me ?
PS: The steps I made are attached
- 3
1
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1
answer
2k
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CMOS Second Order Effects
I'm in a CMOS class and we are currently going through the second order effects of a NMOS. I have a few questions.
When the body isn't connected to the source, the threshold voltage increases. ...
- 159
1
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1
answer
2k
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How diffusion constant vary with temperature in Semiconductors?
Diffusion constant = Mobility*Thermal Voltage
*Where,Thermal voltage = T/11600*
From above equation it is clear that Diffusion constant should ...
- 19
-2
votes
1
answer
1k
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What is Minority Carrier Storage Time?
I know that Minority Carrier Life-Time is the time difference Between generation of minority carrier & their Recombination. I am bit Confused Between Minority Carrier Storage Time & Minority ...
- 19
2
votes
1
answer
98
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How to design Digital logic gate using TFET logic?
In my recent project, I need to design digital logic gates using TFET instead of CMOS logic.
Can someone Suggest any simulator or procedure which support design using TFET logic?
- 558
2
votes
2
answers
574
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When does Direct Source-Drain tunneling become a problem?
Because of the probabilistic nature of quantum mechanics, direct source-drain tunneling is bound to happen as a result of CMOS scaling. The smaller the transistors become, the more tunneling occurs.
...
- 377