Why does higher temperature decrease NMOS threshold voltage?

Question

The threshold voltage of a MOSFET decreases as temperature increases.

I don't understand this. Consider an n-type MOSFET that is fabricated in a p-doped silicon substrate. For a channel/inversion layer to be formed under the gate, the holes in the p-substrate directly under the gate must be fully depleted.

As temperature increases, the number of free electrons (minority carrier here) and free holes (majority carrier here) increases. However, since this is a p-type substrate, the free holes are the majority carrier and so should increase in a much greater amount than the free electrons.

Now there are more free holes in the p-substrate directly under the gate. These free holes must be depleted before a channel can be formed. Hence, Vth should increase as there are more free holes to deplete!

Answer 1

In semiconductors, most electrons are bound to the lattice and cannot contribute to conduction. Electrons that might conduct can do so only after surmounting an energy barrier. It is my understanding that the gate source voltage reduces the height of the energy barrier as it becomes more positive.

As the temperature increases the electrons become more energetic and so the relative barrier is lower so less gate-source voltage is required. Thus the threshold voltage is lower.

Because the electrons (and so is the lattice) are more energetic there are more collisions that impede charge flow. This manifests as a higher RDSon at higher temperatures.

This is my understanding as a lowly user of semiconductors.