Questions tagged [rise-time]
Anything related to the rise time of a signal. The rise time is a parameter used to characterize abrupt transitions in a signal waveform. It is usually defined as the time needed by the signal to go from the 10% to the 90% of the level it attains at the end of the transition.
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How to speed up rise time on logic shifter?
I am trying to boost a 3.3V data signal to 5V, and I'm using a logic shifter to achieve that. Basically, I'm trying to drive WS2813 LEDs, and the data line needs something close to Vdd (5V) to read ...
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Meaning of time parameters in control theory
I know in control theory there are different time parameters, but I'm not sure why they are used and defined that way, with my main doubts being about rise time; definitions from here:
Delay time (td)...
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Does time constant or rise time concept apply in transformers as well? [closed]
I am new to electrical engineering.
I have made a transformer where I kept one primary and two secondaries, there's an air gap between the primary leg and secondaries on toroidal core, you can watch ...
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Rise time and fall time of P-Channel FET
I have tied the gate to a 10 kilo-ohm pull-up resistor, as shown below. The FET I am using is the NTD2955T4G. The control signal is a control PCB. The output of the control PCB has a low side switch ...
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Ideal op-amp used as a digital buffer: rise time
Vo = Vin, so the rise time for both should be the same, but the capacitor takes some time charging.
How can I find the charging time without any other information here?
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Long rise time on UART RX line
I'm attempting to replace a controller unit (based on an STM32F1) with my own design (based on ESP32), but I'm stuck at the UART RX (seen from the controller side). The rise time of the signal is too ...
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Unexpected voltage spikes at output of PFET on falling edge
I have the circuit shown below:
I want this circuit to switch between 2.5V and 3.6V at the drain of the PFET when I input a square wave into the gate of the PFET.
I would expect that this circuit ...
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LVDS rise/fall time measurements - confused
In a document I found they mention that the rise/fall times are measured over 20-80% of the signal. They mention that the common mode is 1.2V with a output voltage swing of 350mV.
This all makes sense,...
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Root Sum Square
Can anyone in a simple way explain why this formula works. It is the Root Sum of Squares where you square your values then add together then take the square root. It seems to be used quite a lot in ...
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Limiting PWM rise and fall time
We're generating a PWM signal at about 2000 Hz whose rise and fall times we need to limit to about 40 us, so it can pass through ordinary audio stages without distortion / ringing.
The PWM signal is 0-...
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Rise time vs Slew Rate
I am using this device which is a LS1046. It list slew rate as 1V/ns to 4V/ns.
It is measured over a region of .35XOVDD to .65XOVDD where OVDD is 1.8V
So over the range of .63V to 1.17V which is .54V
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What determines the rise time of a digital signal?
What are the factors that determine or affect the rise time of a digital signal?
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Using a pull-up resistor and considering rise time for IC input
I have a FPGA based design in which the FPGA is interfaced with several ICs. The I/Os of the FPGA and most of the ICs are 3.3V, except from one where the I/Os are 1.8V. While there is no problem for ...
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Alternative to optocoupler in circuit design
I have designed a circuit that drives a +/- 20 to 30 peak to peak external signal received as an input to 16 different outputs.
Another requirement is that I have to be able to switch the state of ...
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Problem with the fall time of op-amp
I am designing a "simple" current source using an op-amplifier. My question is why is my fall time looking like that:
What do I need to reduce the fall time? Here is the schematic:
