All Questions
7
questions
1
vote
1
answer
43
views
Trying to figure out rise/fall times for different load conditions
I have a device that requires a certain rise/fall time for its input clock. It specs a .7ns rise and fall time with a 20% to 80% measurement at a Cin=6pf. I should note that the spec rise/fall time ...
- 217
2
votes
1
answer
419
views
Clock line of SDIO bus has worse rise/fall time than rest of bus
I have an ATWILC3000 wifi module connected to a Raspberry Pi Compute Module 3+ over 4-bit SDIO. It's throwing a lot of bus errors at higher frequencies (currently running at 1 MHz for stability when ...
- 1,723
0
votes
2
answers
843
views
Timing specifications in a communication protocol
I am having this I2C EEPROM Chip from Onsemi - CAT24C
In table 6, AC Characteristics of the datasheet, only the Minimum time is provided for the SCL clock low and high period.
My questions :
Not ...
user220456
0
votes
1
answer
55
views
TLC5926IPWPR Clock width
I'm using the TLC5926IPWPR in a design. It uses an SPI interface. The TLC5926IPWPR chip is on a separate PCB than the MCU that is controlling it. The Clock and SDO pin must go through a cable about a ...
- 314
2
votes
1
answer
1k
views
No Feasible Entries for Subprogram "rising_edge"
It's my first time coding in VHDL and I ran to some problem I have absolutely no idea how to solve. When I try to compile my code in modelsim it gives me "No Feasible Entries for Subprogram ...
- 135
0
votes
1
answer
119
views
Rise/Fall time of GP Pins
Are rise/fall times typically affected by the clock speed. That is if I have a AVR at 16 MHz will it have a different rise/fall time than the same AVR at 32kHz?
- 368
5
votes
2
answers
875
views
Square wave generator has nigh-useless output
I have a system that was designed for testing digital components. I have a device in the system which is used for generation and acquisition of digital signals. Now, I will happily admit to not ...
- 476