All Questions
3
questions
0
votes
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answers
322
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Using a pull-up resistor and considering rise time for IC input
I have a FPGA based design in which the FPGA is interfaced with several ICs. The I/Os of the FPGA and most of the ICs are 3.3V, except from one where the I/Os are 1.8V. While there is no problem for ...
- 153
0
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2
answers
219
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Minimizing pulled open collector output rise time on 74LS09
I have a circuit that calls for one open collector buffer for driving a shared line (/WAIT via Zilog Z80) and one typical AND gate. I've consolidated these into a single 74LS09 open collector quad 2-...
- 127
3
votes
1
answer
727
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How to correctly set logical high level on a PS/2 port?
I'm trying to make a keyboard emulator on ATmega16A. I'm currently implementing logical low as output-zero, and, since the host(?) is supposed to pull up the line, I send logical high state as input ...
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