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Neurmorphic Architectures
Kenneth Rice and Tarek Taha
Clemson University
Historical Highlights
Analog VLSI
 Carver Mead and his
students pioneered the
development aVLSI
technology for use in
neural circuits
 They developed a silicon
retina which
electronically emulated
the first 3 layers of the
retina
Image from [3]
Artificial Neural Network Chips
 Early neuromorphic architectures were artificial neural
network chips
 Examples:
 ETANN : (1989) Entirely analog chip that was designed
for feed forward artificial neural network operation.
 Ni1000 : (1996) Significantly more powerful than
ETANN, however has narrower functionality

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Neuromorphic circuits are typically used to emulate cortical structures and to explore principles of computation of the brain. But they can also be used to implement convolutional and deep networks. Here we demonstrate a proof of concept, using our latest multi-core and on-line learning reconfigurable spiking neural network chips.

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Machine Learning
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This document provides an overview of Mahdi Hosseini Moghaddam's background and work applying machine learning and cognitive computing for intrusion detection. It discusses his education in computer science and engineering and awards. It then outlines the goals of the presentation to discuss real-world applications of machine learning rather than scientific details. The document proceeds to discuss problems with current intrusion detection systems, introduce concepts in machine learning and cognitive computing, and describe Mahdi's methodology and architecture for a hardware-based machine learning system using a cognitive processor to enable fast intrusion detection.

Artificial Neural Network and its Applications
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Abstract This report is an introduction to Artificial Neural Networks. The various types of neural networks are explained and demonstrated, applications of neural networks like ANNs in medicine are described, and a detailed historical background is provided. The connection between the artificial and the real thing is also investigated and explained. Finally, the mathematical models involved are presented and demonstrated.

artificial neural networks
SYNAPSE-1 System Architecture
Image from [6]
SYNAPSE-1 is a
modular system
arranged as a 2D
array of MA16s,
weight memories,
data units, and a
control unit
Modern Architectures:
Custom Circuits
Neurogrid
 (2005) Neurogrid is a multi-chip system developed by
Kwabena Boahen and his group at Stanford University
[9]
 Objective is to emulate neurons
 Composed of a 4x4 array of Neurocores
 Each Neurocore contains a 256x256 array of neuron
circuits with up to 6,000 synapse connections
The FACETS Project
 (2005) Fast Analog
Computing with Emergent
Transient States (FACETS)
 A project designed by an
international collective of
scientists and engineers
funded by the European
Union
 Recently developed a chip
containing 200,000 neuron
circuits connected by 50
million synapses.
Image from [9]

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Recurrent Neural Networks (RNNs) represent the reference class of Deep Learning models for learning from sequential data. Despite the widespread success, a major downside of RNNs and commonly derived ‘gating’ variants (LSTM, GRU) is given by the high cost of the involved training algorithms. In this context, an increasingly popular alternative is the Reservoir Computing (RC) approach, which enables limiting the training algorithm to operate only on a restricted set of (output) parameters. RC is appealing for several reasons, including the amenability of being implemented in low-powerful edge devices, enabling adaptation and personalization in IoT and cyber-physical systems applications. This webinar will introduce Reservoir Computing from scratch, covering all the fundamental design topics as well as good practices. It is targeted to both researchers and practitioners that are interested in setting up fastly-trained Deep Learning models for sequential data.

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The document provides an overview of artificial neural networks and biological neural networks. It discusses the components and functions of the human nervous system including the central nervous system made up of the brain and spinal cord, as well as the peripheral nervous system. The four main parts of the brain - cerebrum, cerebellum, diencephalon, and brainstem - are described along with their roles in processing sensory information and controlling bodily functions. A brief history of artificial neural networks is also presented.

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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.

Torres-Huitzil: FPGA Model
 Torres-Huitzil et. al (2005) designed an hardware
architecture for a bio-inspired neural model for
motion estimation.
 Architecture has 3 basic components which perform
spatial, temporal, and excitatory-inhibitory
connectionist processing.
 Observed approximately 100 x speedup over Pentium 4
processor implementation for 128x128 images
CMOL based design
 Developed by Dan Hammerstrom
HTM on FPGAs
 Implemented on a Cray XD1
Level 2
AMD
Processor
Level 1
AMD
Processor
FPGA PE
PE FPGA PE
PE
AMD
Processor
Off-Chip
Memory
Off-Chip
Memory
Level 2
AMD
Processor
Level 1
Level 3
AMD
Processor
FPGA PE
PE FPGA PE
PE
AMD
Processor
Off-Chip
Memory
Off-Chip
Memory
PEs on FPGA
To Host Processor
Interface and
Reconfiguration
Logic
Level 2
Node
Pxu
λ/π
Addr Addr (A)
Memory
Access Unit
A D
Data (D)
Data
To External
Memory
Interface
Processing Element (PE)
λ/π
Pxu
λ
A D
A
D
λ
Pxu
λ/π
Level 1
Node
A D
A
D
A D
Pxu
λ
λ/π
Level 1
Node
A
D
Pxu
λ
λ/π
Level 1
Node
A D
A
D
Level 1
Node
To Host Processor
Interface and
Reconfiguration
Logic
Level 2
Node
Pxu
λ/π
Addr Addr (A)
Memory
Access Unit
A D
Data (D)
Data
To External
Memory
Interface
Processing Element (PE)
λ/π
Pxu
λ
A D
A D
A
D
A
D
λ
Pxu
λ/π
Level 1
Node
A D
A
D
A D
Pxu
λ
λ/π
Level 1
Node
A
D
Pxu
λ
λ/π
Level 1
Node
A D
A D
A
D
A
D
Level 1
Node
To Host Processor
Interface and
Reconfiguration
Logic
Level 2
Node
Pxu
λ/π
Addr Addr (A)
Memory
Access Unit
A D
Data (D)
Data
To External
Memory
Interface
Processing Element (PE)
λ/π
Pxu
λ
A D
A
D
λ
Pxu
λ/π
Level 1
Node
A D
A
D
A D
Pxu
λ
λ/π
Level 1
Node
A
D
Pxu
λ
λ/π
Level 1
Node
A D
A
D
Level 1
Node
To Host Processor
Interface and
Reconfiguration
Logic
Level 2
Node
Pxu
λ/π
Addr Addr (A)
Memory
Access Unit
A D
Data (D)
Data
To External
Memory
Interface
Processing Element (PE)
λ/π
Pxu
λ
A D
A D
A
D
A
D
λ
Pxu
λ/π
Level 1
Node
A D
A
D
A D
Pxu
λ
λ/π
Level 1
Node
A
D
Pxu
λ
λ/π
Level 1
Node
A D
A D
A
D
A
D
Level 1
Node

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Kalman filter have been used for the estimation of instantaneous states of linear dynamic systems. It is a good tool for inferring of missing information from noisy measurement. The quantum neural network is another approach to the merging of fuzzy logic with the neural network and that by the investment of quantum mechanics theory in building the structure of neural network. The gradient descent algorithm has been used, widely, in training the neural network, but the problem of local minima is one of the disadvantages of this algorithm. This paper presents an algorithm to train the quantum neural network by using the extended kalman filter.

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Artificial neural networks can achieve high computation rates by employing a massive number of simple processing elements with a high degree of connectivity between the elements. Neural networks with feedback connections provide a computing model capable of exploiting fine- grained parallelism to solve a rich class of complex problems. In this paper we discuss a complex series-parallel system subjected to finite common cause and finite human error failures and its reliability using neural network method.

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Large Scale Simulations
 IBM:
 Blue Brain Project: IBM & EPFL (Switzerland)
 IBM Almaden Research Center
 Los Alamos National Lab
 Air Force Research Laboratory (Rome, NY)
 Academia:
 Portland State University
 Royal Institute of Technology (KTM, Sweden)
AFRL PS3 Cluster
For more information
 Visit Institute of Neuromorphic Engineering:
 http://www.ine-web.org/
References
[1] Neuromorphic, <http://en.wikipedia.org/wiki/Neuromorphic>.
[2] Hammerstrom, D. “A Survey of Bio-Inspired and Other Alternative
Architectures,” in Waser, Rainer (ed.) Nanotechnology. Volume 4:
Information technology II. Weinheim: Wiley-VCH, pp. 251-282, 2006.
[3] Carver Mead, <http://en.wikipedia.org/wiki/Carver_Mead>
[4] Holler, M., et al. “An Electrically Trainable Artificial Neural Network
(ETANN) with 10240 "Floating Gate” Synapses,” International Joint
Conference on Neural Networks, 1989.
[5] Nestor, I., Ni1000 Recognition Accelerator - Data Sheet, 1-7, 1996.
[6] Ramacher, U. et al. “SYNAPSE-1: a high-speed general purpose parallel
neurocomputer system, “ IPPS ( 774-781). 1995.

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This document introduces neural networks and neuro-DEVS. It defines artificial neural networks and provides examples of single neuron and multi-layer network structures. It describes different types of neural networks including perceptrons, multi-layer perceptrons, backpropagation networks, Hopfield networks, and Kohonen feature maps. It discusses areas where neural networks can be useful and their limitations. It outlines the advantages of using neural networks and describes three main applications. It provides an overview of the neuro-atomic model and its use in DEVS simulations, giving an example of a solar energetic system model that uses a neural network as a sub-component.

References
[7] R. Serrano-Gotarredona, T. et al. “A Neuromorphic Cortical Layer Microchip for
Spike Based Event Processing Vision Systems,” IEEE Trans. on Circuits and Systems,
Part-I. Vol. 53, No. 12, pp. 2548-2566, December 2006.
[8] Serrano-Gotarredona, R., et al. “AER Building Blocks for Multi-Layer Multi-Chip
Neuromorphic Vision Systems,” , Advances in Neural Information Processing
Systems (NIPS), 18: 1217-1224, Dec, Y. Weiss and B. Schölkopf and J. Platt (Eds.), MIT
Press, 2005
[9] Brains in Silicon,<http://www.stanford.edu/group/brainsinsilicon/index.html >.
[10] FACETS: Fast Analog Computing with Emergent Transient States,
<http://facets.kip.uni-heidelberg.de/index.html>.
[11] Graham-Rowe, D. “Building a Brain on a Silicon Chip,” in Technology Review,
March 25, 2009. [Online]. Available:
<http://www.technologyreview.com/computing/22339/page1/ >. [ Accessed March
28, 2009].
[12] C. Torres-Huitzil, et. al. “On-chip Visual Perception of Motion: A Bio-inspired
Connectionist Model on FPGA, “ Neural Networks Journal, 18(5-6):557-565, 2005.

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taha.ppt

  • 1. Neurmorphic Architectures Kenneth Rice and Tarek Taha Clemson University
  • 3. Analog VLSI  Carver Mead and his students pioneered the development aVLSI technology for use in neural circuits  They developed a silicon retina which electronically emulated the first 3 layers of the retina Image from [3]
  • 4. Artificial Neural Network Chips  Early neuromorphic architectures were artificial neural network chips  Examples:  ETANN : (1989) Entirely analog chip that was designed for feed forward artificial neural network operation.  Ni1000 : (1996) Significantly more powerful than ETANN, however has narrower functionality
  • 5. SYNAPSE-1 System Architecture Image from [6] SYNAPSE-1 is a modular system arranged as a 2D array of MA16s, weight memories, data units, and a control unit
  • 7. Neurogrid  (2005) Neurogrid is a multi-chip system developed by Kwabena Boahen and his group at Stanford University [9]  Objective is to emulate neurons  Composed of a 4x4 array of Neurocores  Each Neurocore contains a 256x256 array of neuron circuits with up to 6,000 synapse connections
  • 8. The FACETS Project  (2005) Fast Analog Computing with Emergent Transient States (FACETS)  A project designed by an international collective of scientists and engineers funded by the European Union  Recently developed a chip containing 200,000 neuron circuits connected by 50 million synapses. Image from [9]
  • 9. Torres-Huitzil: FPGA Model  Torres-Huitzil et. al (2005) designed an hardware architecture for a bio-inspired neural model for motion estimation.  Architecture has 3 basic components which perform spatial, temporal, and excitatory-inhibitory connectionist processing.  Observed approximately 100 x speedup over Pentium 4 processor implementation for 128x128 images
  • 10. CMOL based design  Developed by Dan Hammerstrom
  • 11. HTM on FPGAs  Implemented on a Cray XD1 Level 2 AMD Processor Level 1 AMD Processor FPGA PE PE FPGA PE PE AMD Processor Off-Chip Memory Off-Chip Memory Level 2 AMD Processor Level 1 Level 3 AMD Processor FPGA PE PE FPGA PE PE AMD Processor Off-Chip Memory Off-Chip Memory
  • 12. PEs on FPGA To Host Processor Interface and Reconfiguration Logic Level 2 Node Pxu λ/π Addr Addr (A) Memory Access Unit A D Data (D) Data To External Memory Interface Processing Element (PE) λ/π Pxu λ A D A D λ Pxu λ/π Level 1 Node A D A D A D Pxu λ λ/π Level 1 Node A D Pxu λ λ/π Level 1 Node A D A D Level 1 Node To Host Processor Interface and Reconfiguration Logic Level 2 Node Pxu λ/π Addr Addr (A) Memory Access Unit A D Data (D) Data To External Memory Interface Processing Element (PE) λ/π Pxu λ A D A D A D A D λ Pxu λ/π Level 1 Node A D A D A D Pxu λ λ/π Level 1 Node A D Pxu λ λ/π Level 1 Node A D A D A D A D Level 1 Node To Host Processor Interface and Reconfiguration Logic Level 2 Node Pxu λ/π Addr Addr (A) Memory Access Unit A D Data (D) Data To External Memory Interface Processing Element (PE) λ/π Pxu λ A D A D λ Pxu λ/π Level 1 Node A D A D A D Pxu λ λ/π Level 1 Node A D Pxu λ λ/π Level 1 Node A D A D Level 1 Node To Host Processor Interface and Reconfiguration Logic Level 2 Node Pxu λ/π Addr Addr (A) Memory Access Unit A D Data (D) Data To External Memory Interface Processing Element (PE) λ/π Pxu λ A D A D A D A D λ Pxu λ/π Level 1 Node A D A D A D Pxu λ λ/π Level 1 Node A D Pxu λ λ/π Level 1 Node A D A D A D A D Level 1 Node
  • 13. Large Scale Simulations  IBM:  Blue Brain Project: IBM & EPFL (Switzerland)  IBM Almaden Research Center  Los Alamos National Lab  Air Force Research Laboratory (Rome, NY)  Academia:  Portland State University  Royal Institute of Technology (KTM, Sweden)
  • 15. For more information  Visit Institute of Neuromorphic Engineering:  http://www.ine-web.org/
  • 16. References [1] Neuromorphic, <http://en.wikipedia.org/wiki/Neuromorphic>. [2] Hammerstrom, D. “A Survey of Bio-Inspired and Other Alternative Architectures,” in Waser, Rainer (ed.) Nanotechnology. Volume 4: Information technology II. Weinheim: Wiley-VCH, pp. 251-282, 2006. [3] Carver Mead, <http://en.wikipedia.org/wiki/Carver_Mead> [4] Holler, M., et al. “An Electrically Trainable Artificial Neural Network (ETANN) with 10240 "Floating Gate” Synapses,” International Joint Conference on Neural Networks, 1989. [5] Nestor, I., Ni1000 Recognition Accelerator - Data Sheet, 1-7, 1996. [6] Ramacher, U. et al. “SYNAPSE-1: a high-speed general purpose parallel neurocomputer system, “ IPPS ( 774-781). 1995.
  • 17. References [7] R. Serrano-Gotarredona, T. et al. “A Neuromorphic Cortical Layer Microchip for Spike Based Event Processing Vision Systems,” IEEE Trans. on Circuits and Systems, Part-I. Vol. 53, No. 12, pp. 2548-2566, December 2006. [8] Serrano-Gotarredona, R., et al. “AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems,” , Advances in Neural Information Processing Systems (NIPS), 18: 1217-1224, Dec, Y. Weiss and B. Schölkopf and J. Platt (Eds.), MIT Press, 2005 [9] Brains in Silicon,<http://www.stanford.edu/group/brainsinsilicon/index.html >. [10] FACETS: Fast Analog Computing with Emergent Transient States, <http://facets.kip.uni-heidelberg.de/index.html>. [11] Graham-Rowe, D. “Building a Brain on a Silicon Chip,” in Technology Review, March 25, 2009. [Online]. Available: <http://www.technologyreview.com/computing/22339/page1/ >. [ Accessed March 28, 2009]. [12] C. Torres-Huitzil, et. al. “On-chip Visual Perception of Motion: A Bio-inspired Connectionist Model on FPGA, “ Neural Networks Journal, 18(5-6):557-565, 2005.

Editor's Notes

  1. Developed the first neural chips
  2. Developed the first neural chips
  3. Developed the first neural chips
  4. ETANN: Because of the analog nature, chip was susceptible to voltage fluctuations.
  5. Developed the first neural chips
  6. http://www.stanford.edu/group/brainsinsilicon/index.html
  7. http://facets.kip.uni-heidelberg.de/index.html Like Neurogrid, has the objective to emulate neurons with electrical components.
  8. They synthesize the architecture in a FPGA and show that a lot of potential to achieve real-time performance at an affordable silicon area.