Speed up with pipelining

Question

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.

My Solution

Speed up = Old execution time/New execution time

Old execution time = CPI/2.5 = 4/2.5 = 1.6 ns

With pipelining, each instruction needs old execution time * old frequency/new frequency (without pipelining) = 1.6 * 2.5 / 2 = 2 ns

There are 5 stages and when there is no pipeline stall, this can give a speed up of up to 5 (happens when all stages take same number of cycles). So, average execution time = 2 / 5 = 0.4 ns

So, speed up compared to non-pipelined version = 1.6 / 0.4 = 4

Ref: Q: 12.10 http://faculty.washington.edu/lcrum/Archives/TCSS372AF06/HW8.doc

Is this solution correct? The answer to this is given as 3.2

Answer 1

From the link you gave, I found that number of instructions that can be completed in 5 cycles is 4.

So average execution time of pipelined processor = 2/4 =0.5 ns.

So the speed up is 1.6/0.5 = 3.2 :)