MIPS lw latency in pipelining

Question

I'm given stages of a clock cycle in a processor.

 IF     ID     EX     MEM    WB   
250ps  350ps  150ps  300ps  200ps

Now I'm being asked what is the total latency of a LW instruction in a pipelined instruction.

Here's what I know:

The clock cycle time in a pipelined version is 350ps because that's the longest instruction.
The clock cycle time in a non-pipelined version is 1250ps because that's the duration of all the instructions added together.

But how does the "latency of a LW instruction" relate to those times?

Answer 1

Ok I'm pretty sure I figured out the answer which is you take the longest duration of the stages which in this case is 350ps and you multiply it by the amount of stages, in this case 5.
So

350 * 5 = 1750ps

Answer 2

Yes, you are correct with your result. Here is the formula:

(Number of Instructions)(Longest Instruction Time with (Unit)) = Latency(Unit)