I have been reading make manual section 4.14 "Generating Prerequisites Automatically" and "Advanced Auto-Dependencies" from this web page.
I think I understand the section from the make manual but there is one thing that I can't wrap my head around on the webpage I linked:
If you think about it, this re-invocation is really unneeded. Since we know some prerequisite of the target changed, we don't really need the updated prerequisite list in this build. We already know that we're going to rebuild the target, and having a more up-to-date list won't affect that decision.
So instead of doing:
%.P : %.c
$(MAKEDEPEND)
@sed 's/\($*\)\.o[ :]*/\1.o $@ : /g' < $*.d > $@; \
rm -f $*.d; [ -s $@ ] || rm -f $@
include $(SRCS:.c=.P)
They do:
%.o : %.c
@$(MAKEDEPEND)
$(COMPILE.c) -o $@ $<
-include $(SRCS:.c=.P)
But if we know a target prerequisite has changed, don't we have to update de dependency list for that target? And isn't that exactly whats done on the first invocation of make? My understanding is that the files included with the include-statement just looks like:
list.o list.P : list.cc list.h debug.h
What am I not getting here?