In a Makefile, is there any way of making a rule an implicit dependency of all other rules?
Say, for instance, i wanted a rule run whenever the Makefile is run, regardless of which rule is actually being requested. How would i do that?
asked May 18, 2011 at 15:20
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2 Answers
I have no idea why you'd want to do this, but in GNU make you can do this by -include-ing a .PHONY file:
.PHONY: run-always
-include run-always
run-always:
echo "trololol"
answered May 19, 2011 at 11:27
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1+1. I hate Jack Kelly with every fiber of my being, but this is ingenious.– BetaCommented May 19, 2011 at 14:04
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Brilliant...thanks! The only reason i want to do this is to print some instructional text whenever the makefile is run. Commented May 19, 2011 at 15:10
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@Beta: The feeling's mutual, in that friendly-rivalry sort of way. Commented May 20, 2011 at 9:04
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1Friendly riv... that's the kind of nemesis you think I am? Oh, it's on. I'm going to go kill one of my henchmen, maybe take a little "me time", then it's on.– BetaCommented May 20, 2011 at 18:56
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1I don't see why you wouldn't want to do something, but bravo for having the solution. Commented May 21, 2011 at 5:12
Include a wildcard rule:
%: mydependency
I've tried this, the following makefile is a proof of concept
all: a b
a:
touch $@
%: ccc
#
ccc::
touch ccc
Note the use of
In order to prevent the dependency from building unconditionally each time, you might want to make it an indirect dependency (requirement for the ccc:: rule above, instead of directly on the wildcard rule).
Good luck
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not exactly what i wanted. I'm thinking whether i run "make a" "make b" or "make", 'echo implicit dependency' will run. ` all: a b a: touch $@ b: touch $@ %: echo implicit dependancy ` edit: can't seem to get the
codemini-markdown to work. Commented May 18, 2011 at 16:05 -
@Woodrow: right I cannot parse that comment. Feel free to update your question and leave me a note– seheCommented May 18, 2011 at 18:27