Specifying dependencies on makefile

Question

I hope that this is obvious to someone out there. I am creating a makefile that I need some special compilation for. I have cuda files and c++ files each need to be compiled separately. I want to be able to specify the file and then list the dependencies for the final output in terms of the

CUDA_FILES := file1.cu file2.cu file3.cu
CPP_FILES := file4.cpp file5.cpp

# lots of options

#rules:
all: project1

project1: file1.o file2.o file3.o file4.o file5.o
  $(LD) $(LDLIBS) $^ -o $@

%.o: %.cu
  $(CUDA) $(CUDA_ARCH) $(CUDA_OPTIONS) $(CUDA_INCLUDES) -Xcompiler "$(COMPILER OPTIONS" $^ -o $@

for the line with project1: how do I automatically generate the object list from the files lists to specify as a dependency?

Answer 1

Just list the object files instead of the source files:

$ cat Makefile
OBJS = a.o b.o

foo: a.o b.o
        $(LD) -o $@ $^
$ make
cc    -c -o a.o a.c
cc    -c -o b.o b.c
ld -o foo a.o b.o

Edit: If you don't want to follow this method, use string substitution:

OBJS = $(CUDA_FILES:%.cu=%.o) $(CPP_FILES:%.cpp=%.o)

Answer 2

CUDA_FILES := $(wildcard *.cu)
CC_FILES := $(wildcard *.cpp)

OBJS := $(CUDA_FILES:.cu=.o) $(CC_FILES:.cc=.o)

Answer 3

I would suggest using the more modern string substitution functions, like:

dogCpp := dog.cpp dogSays.cpp
dogObj := $(patsubst %.cpp,%.o,${dogCpp})