Questions tagged [nand]
Use this tag when referring to any circuit that uses NAND gate / NAND logic, or for asking questions relating to NAND gates.
168
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Transistor using base voltage without collector [closed]
I have been trying to make logic gates from transistors. Their collector-emitter parts are connected in series and a LED (with a limiting resistor in series) is inserted in the emitter of the end-...
2
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1
answer
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9T SRAM Circuit Supporting 1-bit Multiplication
I was reading a paper that added a 3T NAND gate, consisting of two NMOS and one PMOS, to the regular 6T SRAM, achieving 1-bit multiplication. However, I'm struggling to understand how the NAND part of ...
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Implementing a circuit using only NAND-2 gates
I have this boolean expression that I got through a k-map twice, once using POS and the other SOP, and I am supposed to implement both minimized f's that I found using only NAND-2 gates but I am very ...
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1
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SPI NAND rewrite issue
I'm using Alliance Memory's AS5F38G04SND-08LIN 8Gbit(1 Gbyte) SLC NAND flash with STM32.
Datasheet
So my question is, Can I re-write a page with data already in it? Page size is 4096 bytes.
For ...
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2
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How does moving an input signal node closer to the output node reduce parasitic capacitance
So I have been studying about logic gates designed using the CMOS family and in my professors notes it says "Move NMOSFET-B closer to output node, without changing the functionality , to reduce ...
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Some chips (probably DRAM) on NVMe SSD are lower than others, resulting heatsink having no contact with those chips after installation
I believe most of the NVMe SSD heatsinks' contact surface is just one flat piece, but not all the chips on the NVMe SSDs have the same height.
From my recent observation, there are air gaps between ...
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2
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2
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288
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NAND gate with two vs. one BJT transistor(s)
Why is everybody discourage from this paired NAND BJT Transistor "design"? I already saw a few posts where somebody asked something about the paired BJT NAND "design" and the ...
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Current flow in PMOS when not active
how can it be that Q2 is active when VA and VB are HIGH?
If I understand correctly, a current (shown in yellow) should flow...
But that is in my understanding not possible because both NMOS are ...
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170
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Chaining NAND gates does not work and results in wrong simulation with LTspice
I started building basic logic gates. I wanted to start basic and understandable so I started building some NAND gates just using two transistors. On its own hooked up to a switch and a LED they work ...
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Should I glue BGA chips in the corners before soldering them with hot air?
I have often see ball grid array (BGA) chips, mostly those from CPUs or GPUs, being glued around in the corners with some red glue or to the perimeter with a translucent one.
Having to manually solder ...
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MOSFET circuit truth table
In the attached image you can find a simple circuit with two self blocking N channel MOSFETs. If the gate is powered they conduct. So my truth table looks like a AND operation. Why is this wrong? Why ...
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"Path to ground with no resistance!" error when trying to simulate a circuit
I'm trying to simulate a NAND gate using transistors and I have remade the circuit as it was in the notebook, but the simulator shows me the error in the title. This is the circuit scheme:
What is ...
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Can the internal FET be disabled?
In this device, can the internal FET be disabled for the CRD_PWR pin?
Can the CRD_PWR pin be left floating?
user220456
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What should I fix in my settings in PSpice for simulation?
I am trying to build a D flip-flop from CMOS NAND gates.
This is the CMOS circuit to be built with NAND gates:
I can simulate NAND gate logic like this, and it works:
1 0 = 1,
0 1 = 1,
0 0 = 1,
1 1 = ...
0
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3
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Schottky TTL current calculator [closed]
I have a problem from university where I have to calculate the I ccl. I am a little bit confused because I don't know how to do it.
The problem says as well that Schottky TTL state is 0 logic (I think ...
