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1 vote
3 answers
112 views

Simple TTL: Is there a way to "detect" a high-z state and easily use that to drive other logic?

I have two TTL style logic chips, call them A and B (*), where the outputs of A are the inputs to B (think: 8 data lines). A has tri-state outputs, so when they are turned off they float. B is an ...
BZo's user avatar
  • 2,131
12 votes
4 answers
2k views

When is it appropriate to mix 74LSxx components with original TTL 74xx?

I spend almost all my tinkering time with 1970s era logic circuits, which use almost all original 7400-series TTL. I do a fair bit of repair and am now starting to design additional logic to work with ...
BZo's user avatar
  • 2,131
3 votes
1 answer
887 views

Why does the 74LS08 see an input logic level even if the inputs are not connected?

I have an 74LS08 (AND gate.) I did not connect any inputs to the IC, but it gives me voltage at the outputs. Should I separate VSS?
Mohammed Al-Elaiwi's user avatar
0 votes
1 answer
277 views

Failsafe circuit for a bistable latching solenoid

I am new to embedded circuits and working on a problem with which I need help. I am using ESP32 soc for controlling a bistable valve using DRV8833 driver module. Please refer to this link for valve ...
Vyshakh P's user avatar
  • 101
0 votes
1 answer
312 views

Frequency counter schematic

I was wondering what's wrong with my Proteus schematic. This schematic is supposed to show the frequency in Hertz on the display but instead only three zeroes are displayed. Is there any component ...
DyBancs's user avatar
3 votes
2 answers
564 views

Is there a standard way of doing a TTL Hi-Z buffer?

I found many examples of IC internals for CMOS Hi-Z (tristate) buffers, but none for the TTL family. I guess that in the TTL world, the "open collector" is much more common, but I see that ...
Steve Schnepp's user avatar
6 votes
4 answers
2k views

What is the methodology behind 555 timer design?

Small circuits in TTL and RTL we could do intuitively, without any methodology. But what about a complex circuit like 555 timer? If it was designed using logic gates, it could be easily deduced by ...
Guilherme's user avatar
  • 395
0 votes
1 answer
38 views

Safety considerations (for parts) for a beginner building with expensive parts

I'm building for the first time (for me) a circuit with an expensive part (a $80 DEC J11 CPU) and would like to know some "safety" tips so I don't inadvertently destroy the thing while playing with it....
davidbak's user avatar
  • 101
0 votes
0 answers
70 views

Clear D flip flop internal logical scheme

I am new in this community and also in logic circuit design and digital electronics. I couldn't find the logical design on the internet for the following D flip flop and i would like to know how it's ...
Razvan Paraschiv's user avatar
0 votes
1 answer
915 views

Why is the output to this 74181 ALU circuit always on?

I recently built an ALU circuit using the 74181 4 bit ALU. The circuit I built is below: simulate this circuit – Schematic created using CircuitLab Please note that the pinout in the ...
zack1544's user avatar
  • 807
0 votes
3 answers
262 views

How to switch one output between two buses

I'm looking to take the output of some registers (e.g. 74LS670) and have them each be able to output either to an A bus or a B bus, obviously only one register can output on each bus at one time. I'...
Michael's user avatar
3 votes
1 answer
1k views

NAND gate output doesn't change to logic 0 when expected

I have this circuit: I'm powering it from an Arduino but that's inconsequential to the operation, it's simply a convenient source of +5v. The orange line is +, black to gnd. If it's not clear from ...
user3662805's user avatar