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I want to check my understanding of how the imm[20|10:1|11|19:12] specifies the bit arrangements in the JAL (jump and link) instruction in RISC-V architecture?

I know the opcode takes up the lower 7-bits, the destination register then uses the next 5-bits, totaling 12 bits. The imm value is then encoded in the remaining higher 20-bits.

Are these remaining 20-bits located in this instruction as follows?

20-bits
<bit 20>, <bits 10 downto 1>, <bit 11>, <bits 19 downto 12>

JAL instruction breakdown in RISC-V opcode table

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1 Answer 1

Reset to default
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They are just 20 bits in the specified order:

enter image description here
From RISC-V User-Level ISA V2.2, p16

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    \$\begingroup\$ WTH is wrong with the distribution of the immediate bits? oO \$\endgroup\$
    – jusaca
    Commented Jul 9 at 6:15
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    \$\begingroup\$ @jusaca it's for quick parallel decode because most of the fields are in fixed position. In fact RISC-V probably has the simplest instruction decoder among the HPC architectures. Read the RISC-V spec, it's explained clearly there along with all the design rationale \$\endgroup\$
    – phuclv
    Commented Jul 9 at 6:45
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    \$\begingroup\$ I will look into the spec, this actually intrigues me. Without having read the spec yet I can't imagine how this layout of bits can be advantegous, but I believe you ;) \$\endgroup\$
    – jusaca
    Commented Jul 9 at 6:59
  • \$\begingroup\$ @phuclv could you comment with a link to a document explaining, I'll happily add to this answer. \$\endgroup\$
    – jonathanjo
    Commented Jul 9 at 8:16
  • \$\begingroup\$ @jusaca \@jonathanjo please check RISC-V: Immediate Encoding Variants, Why are RISC-V S-B and U-J instruction types encoded in this way?, Why does RISC-V 'J-immediate' encode imm[11] in inst[20]? \$\endgroup\$
    – phuclv
    Commented Jul 9 at 10:32

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