I have two TTL style logic chips, call them A and B (*), where the outputs of A are the inputs to B (think: 8 data lines). A has tri-state outputs, so when they are turned off they float. B is an inverting buffer which also offers tri-state outputs (if you toggle off its chip enable)
What I'd ideally like to do is "detect" the high-z state seen at the A outputs and use that state to disable the chip enable for B (thus causing it to go to hi-z on its outputs). This is because, otherwise, when the output of A is floating and "meaningless", the output of B is also meaningless, but will be driven and not predictable.
A is an interface chip that goes into high-z outputs based on internal state, so there's no trivial enable line to A that I can simply also use for B.
I'm a still-learning hobbyist here. This question suggests that using a voltage divider on an output from A can result in three well-known states, which could be used to do other stuff. I'm not sure exactly how, or what would be involved in that? Could someone offer a thought on how they might think about achieving this?
(The backup plan, which seems less elegant, is simply to use pull-ups or downs on all of the inputs to B so that B's outputs may be always-on but are always predictable.)
(*) A is a 6820 PIA and B is a 74LS240, but I don't think that's critical to the question.