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I have two TTL style logic chips, call them A and B (*), where the outputs of A are the inputs to B (think: 8 data lines). A has tri-state outputs, so when they are turned off they float. B is an inverting buffer which also offers tri-state outputs (if you toggle off its chip enable)

What I'd ideally like to do is "detect" the high-z state seen at the A outputs and use that state to disable the chip enable for B (thus causing it to go to hi-z on its outputs). This is because, otherwise, when the output of A is floating and "meaningless", the output of B is also meaningless, but will be driven and not predictable.

A is an interface chip that goes into high-z outputs based on internal state, so there's no trivial enable line to A that I can simply also use for B.

I'm a still-learning hobbyist here. This question suggests that using a voltage divider on an output from A can result in three well-known states, which could be used to do other stuff. I'm not sure exactly how, or what would be involved in that? Could someone offer a thought on how they might think about achieving this?

(The backup plan, which seems less elegant, is simply to use pull-ups or downs on all of the inputs to B so that B's outputs may be always-on but are always predictable.)

(*) A is a 6820 PIA and B is a 74LS240, but I don't think that's critical to the question.

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    \$\begingroup\$ The actual part numbers are relevant. The outputting device might have an output enable or write enable pin. You generally want pull-ups or pull-down when there is a possibility for an undefined state (Hi-Z in your case). \$\endgroup\$
    – Lior Bilia
    Commented Jan 10 at 20:23
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    \$\begingroup\$ You could use a bias network (resistor divider) to push an output pin on A to 1/2VCC and a pair of comparators at, say, 1.1x Vol and 0.9x Voh to give a matching output when neither condition is met but I agree with @LiorBilia to exhaust the search for another potential signal before adding circuitry. \$\endgroup\$
    – vir
    Commented Jan 10 at 20:28
  • \$\begingroup\$ @LiorBilia The part numbers are in the question (at the bottom). As noted, the output state of A (a 6820 PIA) is driven by internal registers and not by external logic or an enable pin. Thanks. \$\endgroup\$
    – BZo
    Commented Jan 10 at 20:36
  • \$\begingroup\$ @vir: Assuming a pair of comparators means another IC or two, plus a few passive support resistors, then it seems like it may be overkill for this situation. (Versus a series of pull up/downs on the intermediate signal lines). But what should I be googling if I'm curious-- "voltage comparator circuit" ? Thanks \$\endgroup\$
    – BZo
    Commented Jan 10 at 20:37
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    \$\begingroup\$ "Comparator circuit" would work but it's really just a component, not a whole lot of circuitry involved with that. A bussed SIP resistor network seems like a good choice here. \$\endgroup\$
    – vir
    Commented Jan 10 at 20:40

3 Answers 3

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It should be sufficient to watch just one of the outputs of the 6820 to detect the high impedance state of the output driver.

schematic

simulate this circuit – Schematic created using CircuitLab

The series resistor ladder R1-R4 sets half of the supply voltage at V_BUS for the high impedance state. In this state none of the MOSFETs is conducting, Vgs is below the threshold. NOE_B is high and so the output driver of the 74LS240 is disabled.

The resistor values are relative low to ensure fast switching of the MOSFETs. Higher values may be acceptable if the circuit deals only with slow I/O signal changes. This was not specified.

The switches SW1 and SW2 represent the tri-state buffers of the ICs.

If NOE_A is low, V_BUS is either high, which turns M2 on, or it is low, which turns M1 on. If M1 is conducting this also turns M2 on via R8, so M2 is always conducting if V_BUS is not in the high impedance state. This reconstructs the original NOE_A signal with around 200 ns delay at NOE_B.

R9 just emulates the estimated output driver strength of the 6820.

R6 and R7 are added to show the high impedance state of the 74240 in the simulator, so V_BUS and OUT_B can be compared in the diagram.

There is a very short glitch in V_G during a high/low level change of V_BUS, but this does not reach NOE_B.

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  • \$\begingroup\$ Thanks for this. This is the kind of explanation I was looking for. It's a bit much for the project at hand given some other tradeoffs, but this is super valuable to understand. I appreciate that you wrote it up with the diagram. Thanks. \$\endgroup\$
    – BZo
    Commented Jan 16 at 0:32
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What I'd ideally like to do is "detect" the high-z state seen at the A outputs and use that state to disable the chip enable for B (thus causing it to go to hi-z on its outputs). This is because, otherwise, when the output of A is floating and "meaningless", the output of B is also meaningless, but will be driven and not predictable.

You could detect a high impedance state if you could use a weak pull up (like 100k - 1MegΩ) to pull the voltage high and detect it. This only works if the input impedance is also high, which it is not, the input impedance changes with voltage and it isn't on the same scale:

enter image description here Datasheet for 74LS240

A weak pull up could be switched in with a fet and then that would pull the line high, however, if the 74LS240 were low, it would probably keep the line low because it would exceed the input current of the weak pull up resistor because of it's 0.2mA current at lower than 0.4V.

So this means that if you wanted to detect a high impedance output, you would also need a high impedance input buffer that has a low current draw when it's low or high. So find one that draws lower current then what you would need for a weak pull up. Also you would need to do an A/B/A test to detect the high impedance. Detect the state, then turn on the pull up and detect the state, then detect the state. If you got a 010 then it's High-Z

Luckily the MC6820 has a very low output impedance (10uA max) when off so it would work.

enter image description here Datasheet for Motorola MC6820

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If a voltage comparator is already too complex, then I can imagine only this imperfect circuit.

The imperfection of this circuit is that it won't react immediately but after a while defined by the RC timer (R1+R2 and C1).

It will also disable B after a long string of 1 if the data is not composed of successions of 0 and 1. This can be a problem or not. If you know the longest string of 1 possible in any message or if every byte is separated by a start bit (0), then it shouldn't be a problem. (To get an immediate and reliable reaction, I'm afraid a much more complex circuit will be needed.)

Every time A output is pulled low, -OE is negative and C1 is empty. Every time it's pulled high, C1 is slowly filling up until a low bit is transmitted again. When it's either pulled high long enough to consider that there is no transmission going on or high Z, C1 is filled and OE becomes positive. While the A output state is high Z but C1 is still not at a positive level, D2 allows to keep B input high until -OE is positive. Thus avoiding unpredictable B output. D1 and D2 prevent C1 to be filled uselessly faster when output A is high. Component values are not exact and should be established after calculation. But they give an idea of the proportions.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Thank you for this. I think the characteristics of it don't meet my need but I don't really understand it immediately so I'm going to spend some time thinking about how this works. A voltage comparator circuit is not necessarily too complex. Given that it seems to be a plausible solution, I will try to sketch that out and maybe ask elsewhere here for comments/critique. Thanks \$\endgroup\$
    – BZo
    Commented Jan 10 at 22:00
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    \$\begingroup\$ In this circuit, I assume that B is disabled when OE is high. \$\endgroup\$
    – Fredled
    Commented Jan 10 at 22:05

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