I am new in this community and also in logic circuit design and digital electronics. I couldn't find the logical design on the internet for the following D flip flop and i would like to know how it's made. I would like to simulate its functionality in Wronex and i have to know of what logic gates it is composed and also how they are linked. All i know is that it is part of the SN54175 TTL.
\$\begingroup\$
\$\endgroup\$
2
-
1\$\begingroup\$ You might look at the 74LS74 datasheet for guidance. \$\endgroup\$– Peter BennettCommented Jun 5, 2018 at 20:08
-
\$\begingroup\$ Within the 54175 the FF is probably NOT implement usin gates, but rather using transistors that more or less function as gates, but are 'merged together' to reduce the component count. But a google serach will turn up equivalent logic circuits. \$\endgroup\$– Wouter van OoijenCommented Jun 5, 2018 at 21:00
Add a comment
|