All Questions
18
questions
0
votes
0
answers
47
views
SOC booting FPGA configuration file
I have some understanding on embedded system booting process, which includes step wise execution of:
ROM boot loader.
First stage boot loader - internal to SOC.
Second stage boot loader - stored on ...
- 1
0
votes
3
answers
558
views
"ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources." in newest Vivado
I am following section "Baseline Vivado project" in page 165-170 of book "Architecting High-Performance Embedded Systems: Design and build high-performance real-time digital systems ...
- 21
0
votes
1
answer
148
views
On Chip Peripheral Emulation - How to accomplish communication with an emulated peripheral that relies on bidirectional signals in between?
I recently asked some questions for an application in hope to gain more clarity on how to accomplish an emulation of an input device peripheral (in my case an input mouse) in simulation. Following ...
- 171
1
vote
1
answer
151
views
What is the easiest way to replace a design inside an Intel Cyclone SoC? [closed]
I would like to integrate my VHDL submodule to the FPGA fabric of an Intel Cyclone SoC and make it communicating with an App on its Linux.
There is lot of documentation on the internet but I am not ...
- 35
1
vote
1
answer
177
views
Two pins on ADV7123 Video DAC is tied to ground
Apologies if the question doesn't make any sense. I'm self-taught and very new to Electrical Engineering.
I'm working on a little project with a DE1-SoC FPGA development board and found out that the ...
- 113
0
votes
2
answers
230
views
Programmable Microcontrollers vs. SoC Devices [closed]
Context:
I essentially don't have a strong electrical engineering background. My knowledge consists in playing around with Arduino based microcontrollers or Raspberry Pis or equivalent SoCs.
Question:...
- 101
0
votes
0
answers
157
views
C code for DDR Access in Xilinx SoC devices
In my design, I want to write to DDR and then I want to fetch the data from DDR memory and then pass them to FPGA to be processed, after that, the data will be written back to DDR memory.I am using ...
0
votes
0
answers
76
views
Cyclone V SE use FPGA to add additional HPS RAM
As near as I can tell, the Cyclone V SE HPS HMC accesses up to 512Mo per chip select, limiting the CPU to 1Go of physical RAM.
I can't find documentation indicating if the HPS can be instructed (i.e. ...
- 133
0
votes
1
answer
522
views
APB PENABLE stays only for one PCLK regardless of PREADY signal
I followed the AMBA 3 APB specification to design my APB slave. Reading from a slave requires several clock cycles to make the data ready for the bus, so I set my PREADY signal for one clock cycle ...
- 3,192
2
votes
1
answer
3k
views
What's the best internal SoC bus?
As far as I know there are two major buses - AMBA/AXI and Wishbone. While AMBA/AXI has proven itself in almost every ARM chip, I didn't find some numbers for Wishbone. Are there any benchmarks or real ...
- 275
0
votes
2
answers
299
views
Change memory content of FPGA SoC (DE1-SoC) using software while .sof (EPCQ) is running on FPGA
I am new to FPGA and FPGA-SoC world. I have a DE1-SoC board. I am doing a project. Hardware design of the project contains a memory block which is initialized using .mif file. I know that we can use ...
0
votes
1
answer
2k
views
Altera equivalent of the Xilinx Zynq UltraScale+ MPSoC [closed]
I'm new the the FPGA world. I was wondering if anybody could tell me the Altera equivalent of the Xilinx Zynq UltraScale+ MPSoC?
I'm looking to buy a development board but it needs to be from Altera....
- 21
0
votes
3
answers
812
views
Comparing FPGA to microcontroller or SOC, assume same functionality, how big can FPGA get?
Looking at this answer to FPGA's vs Microcontrollers --https://electronics.stackexchange.com/a/4393/127001
It mentions that FPGA is space-limited, and MCU is time-limited. So this got me to ...
- 1
2
votes
2
answers
346
views
Access NEON coprocessor from programmable logic in Zynq
For the past few days I've been thinking about the neon coprocessor in the Zynq SoC and I have a question, is it possible to send instructions to the neon from the PL side of the SoC?
Imagine I have ...
- 151
3
votes
1
answer
2k
views
What is the difference between SoC FPGA and 'regular' FPGA?
I've recently developed an interest in implementing projects on top of an FPGA dev board, and wish to purchase one such as the Altera DE1.
Looking in the company's site, I noticed there is another ...
- 155