Voltage drop in NMOS inverter with enhancement load

Question

In the enhancement load NMOS inverter, why is the voltage drop across M2 at least equal to Vth when VIN is low ? Is it because for M2 when VIN is low the voltages VGS = VDS, so VDS > VGS - Vth and M2 is in saturation. Now it can be said that as no current flows through Q2 and Q1 then from the equation:

ID = k(VGS−Vt)^2

If ID = 0 then VGS=Vth.

Is this analysis correct ?

Answer 1

why is the voltage drop across M2 at least equal to Vth when VIN is low?

For M2 to turn on, V(GS) needs to be Vth or more, per definition of Vth. Since M2's gate and drain are connected together, Both V(GS) and V(DS) need to be Vth or more.